HD6433044 Hitachi Semiconductor, HD6433044 Datasheet - Page 131
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HD6433044
Manufacturer Part Number
HD6433044
Description
(HD64 Series) Hitachi Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6433044.pdf
(867 pages)
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Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted
in access to external three-state-access areas.
Bit 1
WC1
0
1
6.2.4 Wait State Controller Enable Register (WCER)
WCER is an 8-bit readable/writable register that enables or disables wait-state control of external
three-state-access areas by the wait-state controller.
WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Wait-State Controller Enable 7 to 0 (WCE7 to WCE0): These bits enable or
disable wait-state control of external three-state-access areas.
Bits 7 to 0
WCE7 to WCE0
0
1
Since WCER enables or disables wait-state control of external three-state-access areas, these
settings are meaningless in single-chip mode (mode 7).
Bit
Initial value
Read/Write
Bit 0
WC0
0
1
0
1
WCE7
Wait-state control disabled (pin wait mode 0)
Wait-state control enabled
Description
R/W
Description
No wait states inserted by wait-state controller
1 state inserted
2 states inserted
3 states inserted
7
1
WCE6
R/W
6
1
Wait-state controller enable 7 to 0
These bits enable or disable wait-state control
WCE5
R/W
5
1
117
WCE4
R/W
4
1
WCE3
R/W
3
1
WCE2
R/W
2
1
WCE1
R/W
1
1
(Initial value)
(Initial value)
WCE0
R/W
0
1
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