A29010 AMICC [AMIC Technology], A29010 Datasheet

A29010

Manufacturer Part Number

A29010

Description

128K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory

Manufacturer

AMICC [AMIC Technology]

Datasheet

1.A29010.pdf (30 pages)

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Preliminary

Features

n 5.0V

n Access times:

n Current:

n Flexible sector architecture

n Embedded Erase Algorithms

General Description

PRELIMINARY

The A29010 is a 5.0 volt-only Flash memory organized as

131,072 bytes of 8 bits each. The 128 Kbytes of data are

further divided into four sectors for flexible sector erase

capability. The 8 bits of data appear on I/O

addresses are input on A0 to A16. The A29010 is offered in

32-pin PLCC, TSOP, and PDIP packages. This device is

designed to be programmed in-system with the standard

system 5.0 volt VCC supply. Additional 12.0 volt VPP is not

required for in-system write or erase operations. However,

the A29010 can also be programmed in standard EPROM

programmers.

The A29010 has the first toggle bit, I/O

whether an Embedded Program or Erase is in progress, or it

is in the Erase Suspend. Besides the I/O

A29010 has a second toggle bit, I/O

addressed sector is being selected for erase. The A29010

also offers the ability to program in the Erase Suspend mode.

The standard A29010 offers access times of 55, 70 and 90

ns allowing high-speed microprocessors to operate without

wait states. To eliminate bus contention the device has

separate chip enable (

enable (

- 55/70/90 (max.)

- 20 mA typical active read current

- 30 mA typical program/erase current

- 1 A typical CMOS standby

- 32 KbyteX4 sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

- Embedded Erase algorithm will automatically erase

A hardware method of protecting sectors to prevent

any inadvertent program or erase operations within

that sector

the entire chip or any combination of designated

sectors and verify the erased sectors

10% for read and write operations

) controls.

(August, 2001, Version 0.3)

), write enable ( WE ) and output

, to indicate whether the

, which indicates

- I/O

toggle bit, the

while the

n Typical 100,000 program/erase cycles per sector

n 20-year data retention at 125 C

n Compatible with JEDEC-standards

n Erase Suspend/Erase Resume

n Package options

The device requires only a single 5.0 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The A29010 is entirely software command set compatible

with

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as input to an internal state-machine that controls the

erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and

erase operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin.

128K X 8 Bit CMOS 5.0 Volt-only,

- Embedded Program algorithm automatically writes

- Reliable operation for the life of the system

- Pinout and software compatible with single-power-

- Superior inadvertent write protection

- Provides a software method of detecting completion

- Suspends a sector erase operation to read data

- 32-pin P-DIP, PLCC, or TSOP(Forward type)

Data

and verifies bytes at specified addresses

supply Flash memory standard

of program or erase operations

from, or program data to, a non-erasing sector, then

resumes the erase operation

the

Uniform Sector Flash Memory

Polling and toggle bits

JEDEC

internal

single-power-supply

AMIC Technology, Inc.

A29010 Series

algorithm

that

Flash

automatically

standard.

Related parts for A29010

A29010 Summary of contents

Page 1

... The 128 Kbytes of data are further divided into four sectors for flexible sector erase capability. The 8 bits of data appear on I/O addresses are input A16. The A29010 is offered in 32-pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5 ...

Page 2

... The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29010 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the ...

Page 3

... STB Timer Pin No. Description A0 - A16 Address Inputs - I/O Data Inputs/Outputs 0 7 Chip Enable CE Write Enable WE Output Enable OE VSS Ground VCC Power Supply 3 A29010 Series I/O - I/O 0 Input/Output Buffers Chip Enable Output Enable STB Data Latch Logic Y-Decoder Y-Gating X-decoder Cell Matrix AMIC Technology, Inc. 7 ...

Page 4

... The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. A29010 Device Bus Operations ...

Page 5

... Output Disable Mode When the disabled. The output pins are placed in the high impedance state. - I/O . Standard A29010 Series - I/O . Standard read cycle timings and 0.5V. (Note that this is a more restricted CC .) The device enters the TTL standby held at V The device requires the IH ...

Page 6

... When using programming equipment, the autoselect mode requires V (11. address pinA9. Address ID pins A6, A1, and A0 must be as shown in Autoselect Table 3. A29010 Autoselect Codes (High Voltage Method) Description A16 - A15 A14 - A10 Manufacturer ID: AMIC X Device ID: A29010 X ...

Page 7

... Erase Suspend). If I/O the reset command returns the device to reading array data (also applies during Erase Suspend A29010 Series goes high, or while in the program command goes high during a program or erase operation, writing 5 AMIC Technology, Inc. ...

Page 8

... PRELIMINARY (August, 2001, Version 0. Increment Address or I/O . See "Write "1", or cause the 5 Note : See the appropriate Command Definitions table for 8 A29010 Series START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data ? Yes Last Address ? ...

Page 9

... When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O Operation Status" for information on these status bits. 9 A29010 Series . Any 3 to determine if the sector erase 3 : Sector Erase Timer" ...

Page 10

... See the appropriate Command Definitions table for erase and I/O together command sequences. 2. See "I/O or I/O status bits, just A29010 Series START Write Erase Command Sequence Data Poll from System No Data = FFh ? Yes Erasure Completed : Sector Erase Timer" for more information. ...

Page 11

... The Erase Resume command is valid only during the Erase Suspend mode. 11. The time between each command cycle has to be less than 50 s. PRELIMINARY (August, 2001, Version 0.3) Table 4. A29010 Command Definitions Bus Cycles (Notes First Second Addr Data Addr Data ...

Page 12

... Several bits, I/O , I/O , I/O , I/O , and I the A29010 to determine the status of a write operation. Table 5 and the following subsections describe the functions of these status bits. I method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. I/O ...

Page 13

... Under both these conditions, the system must issue the to control the read reset command to return the device to reading array data. I A29010 Series and I Toggle Bit II" explains the algorithm Toggle Bit I" subsection. Refer to the 6 vs. I/O ...

Page 14

... Version 0.3) switches from "0" the system can ( Data Polling I/O is "1", the "0", the device 3 is high on the A29010 Series START Read I/O -I Read I/O -I (Note 1) No Toggle Bit = Toggle ? Yes No I ...

Page 15

... VCC+0.5V 2.0V PRELIMINARY (August, 2001, Version 0.3) Table 5. Write Operation Status I/O I (Note 1) Toggle I Toggle 1 No toggle Data Data Toggle I/O 7 20ns 20ns 20ns 20ns 20ns 20ns 15 A29010 Series I/O I/O I (Note 2) (Note 1) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data Data 0 N/A N/A AMIC Technology, Inc. ...

Page 16

... OUT VCC 0.5 V VCC = 5. 12.0 mA, VCC = VCC Min -2.5 mA, VCC = VCC Min -100 A. VCC = VCC Min A29010 Series Min. Typ. Max. Unit 1.0 A 100 A 1 0.4 1.0 mA -0.5 V 0.8 2.0 VCC+0.5 V 10.5 V 12.5 0.45 V 2.4 V Min. ...

Page 17

... Output 0V PRELIMINARY (August, 2001, Version 0.3) Test Setup = Read Toggle and Polling Data t RC Addresses Stable t ACC OEH t CE High-Z 17 A29010 Series Speed -55 -70 -90 Min Max Max Max Min Min Max. 18 ...

Page 18

... See the "Erase and Programming Performance" section for more information. PRELIMINARY (August, 2001, Version 0.3) Description Min. Min. Min. Min. Min. Min. Min. low) Min. Min. Min. Min. Max. Typ. Typ. Min. 18 A29010 Series Speed Unit -55 -70 - ...

Page 19

... Note : PA = program addrss program data, Dout is the true data at the program address. PRELIMINARY (August, 2001, Version 0. WPH A0h PD 19 A29010 Series Read Status Data (last two cycles WHWH1 D Status OUT AMIC Technology, Inc. ...

Page 20

... Note : SA = Sector Address Valid Address for reading status data. PRELIMINARY (August, 2001, Version 0. 555h for chip erase WPH 55h 30h 10h for chip erase 20 A29010 Series Read Status Data WHWH2 In Complete Progress AMIC Technology, Inc. ...

Page 21

... Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. PRELIMINARY (August, 2001, Version 0. Complement Complement Status Data Status Data 21 A29010 Series VA High-Z Valid Data True High-Z True Valid Data AMIC Technology, Inc. ...

Page 22

... PRELIMINARY (August, 2001, Version 0. Valid Status Valid Status (first read) (second read) . Illustration shows first two status cycle after command sequence, last status 6 22 A29010 Series VA VA Valid Status Valid Status (stop togging) AMIC Technology, Inc. ...

Page 23

... Erase Suspend Suspend Read Program and I/O in the section "Write Operation Statue" for 6 2 Description Min. Min. Min. Min. Min. Min. Min. Min. Min. Min. Typ. Typ. 23 A29010 Series Erase Resume Erase Erase Read Complete Speed -55 -70 - ...

Page 24

... PD for program 30 for sector erase 10 for chip erase Typ. (Note 1) Max. (Note 300 3.6 10.8 for further information A29010 Series PA t WHWH1 I/O 7 OUT = Complement of Data Input Array Data. 7 OUT Unit Comments sec Excludes 00h programming prior to erasure (Note 4) ...

Page 25

... Sampled, not 100% tested. 4. Test conditions 1.0MHz A Data Retention Parameter Minimum Pattern Data Retention Time PRELIMINARY (August, 2001, Version 0.3) Description Test Setup Test Setup Test Conditions 150 C 125 C 25 A29010 Series Min. -1.0V VCC+1.0V -100 mA +100 mA -1.0V Typ. Max 7 ...

Page 26

... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Device Under Test PRELIMINARY (August, 2001, Version 0.3) - 0.0 - 3.0 1.5 1.5 5 A29010 Series All others Unit 1 TTL gate 100 0.45 - 2.4 V 0.8, 2.0 V 0.8, 2.0 V Diodes = IN3064 or Equivalent AMIC Technology, Inc. ...

Page 27

... A29010V-90 PRELIMINARY (August, 2001, Version 0.3) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA A29010 Series Standby Current Package Typ 32Pin DIP 32Pin PLCC 1 32Pin TSOP 32Pin DIP 32Pin PLCC 1 32Pin TSOP 32Pin DIP 32Pin PLCC 1 32Pin TSOP AMIC Technology, Inc. ...

Page 28

... E 0.537 0.542 0.547 13.64 E 0.590 0.600 0.610 14.986 1 E 0.630 0.650 0.670 16.002 0.100 - L 0.120 0.130 0.140 3.048 - A29010 Series unit: inches/ Dimensions in mm Nom Max - - 5.334 - - 3.912 4.039 - 0.457 - - 1.270 - - 0.254 - 41.91 42.037 13.767 13.894 15.240 15.494 16 ...

Page 29

... D 0.390 0.410 0.430 9.91 E 0.585 0.590 0.595 14. 0.485 0.490 0.495 12. 0.075 0.090 0.095 1. 0.003 & G are for PC Board surface mount pad pitch A29010 Series unit: inches/ Dimensions in mm Nom Max - - 3. 2.80 2.93 0.71 0.81 0.46 0.54 0.254 0.35 13.97 14.05 11.43 11.51 1.27 1.42 12.95 13.46 10.41 10.92 14.99 15.11 12.45 12.57 2.29 2. 0.075 AMIC Technology, Inc ...

Page 30

... D 0.720 0.724 0.728 18. 0.315 0.319 e 0.020 BSC 0.779 0.787 0.795 19. 0.016 0.020 0.024 0. 0.032 - 0.020 0.003 - A29010 Series unit: inches/ Detail "A" Dimensions in mm Nom Max - - 1.20 - 0.15 1.00 1.05 0.22 0.27 - 0.20 18.40 18.50 - 8.00 8.10 0.50 BSC 20.00 20.20 0.50 0. AMIC Technology, Inc. ...

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