F25L004A-100DIG ESMT [Elite Semiconductor Memory Technology Inc.], F25L004A-100DIG Datasheet - Page 5

• Manufacturer Part Number: F25L004A-100DIG
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, BP1, BP0 bits as long as
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
Elite Semiconductor Memory Technology Inc.
Protection Level
All Blocks
All Blocks
All Blocks
All Blocks
Upper 1/8
Upper 1/4
Upper 1/2
0
Table2 : F25L004A Block Protection Table
BP2
0
0
0
0
1
1
1
1
Status Register Bit
WP
BP1
is high or the
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Block Protection Lock-Down (BPL)
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Block Range
WP
WP pin is driven high (V
Block 4~7
Block 0~7
Block 6~7
Block 0~7
Block 0~7
Block 0~7
Block 7
None
pin driven low (V
Protected Memory Area
Operation Temperature Condition -40
40000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
70000H – 7FFFFH
60000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
Publication Date: Jan. 2009
Revision:
Address Range
IH
IL
), the BPL bit has no effect and its
), enables the Block-Protection
None
1.3
F25L004A
5/33
°
C
~85
°
C