M52S32321A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52S32321A-10BG Datasheet - Page 16
M52S32321A-10BG
Manufacturer Part Number
M52S32321A-10BG
Description
512K x 32Bit x 2Banks Synchronous DRAM
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
1.M52S32321A-10BG.pdf
(29 pages)
- Current page: 16 of 29
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ESMT
Page Read Cycle at Different Bank @ Burst Length=4
DQ
*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.
Elite Semiconductor Memory Technology Inc.
A10/AP
CLOCK
ADDR
DQM
CL=2
CL=3
RAS
CAS
CKE
WE
CS
BA
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
*Note1
0
Row Active
(A-Bank)
RAa
RAa
1
2
3
(A-Bank)
Read
CAa
4
Row Active
(B-Bank)
RBb
RBb
5
QAa0
6
QAa1
QAa0
7
(B-Bank)
Read
QAa1
QAa2 QAa3
CBb
8
QAa2
9
QBb0
QAa3
HIGH
10
QBb1 QBb2
QBb0
11
(A-Bank)
Read
QBb1
CAc
12
QBb3
QBb2 QBb3
13
(B-Bank)
Read
QAc0
CBd
14
Revision : 1.5
Publication Date : Jan. 2009
QAc1 QBd0
QAc0
15
M52S32321A
(A-Bank)
Read
CAe
QAc1 QBd0
16
QBd1
17
Precharge
(A-Bank)
*Note2
QAe0
QBd1 QAe0
18
QAe1
16/29
19
QAe1
: Don't care
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