ISPLSI5128VE LATTICE [Lattice Semiconductor], ISPLSI5128VE Datasheet - Page 18

• Manufacturer Part Number: ISPLSI5128VE
• Description: In-System Programmable 3.3V SuperWIDE High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

Power consumption in the ispLSI 5128VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of product terms
used. The product terms have a fuse-selectable speed/
power tradeoff setting. Each group of five product terms
has a single speed/power tradeoff control fuse that acts
on the complete group of five. The fast “high-speed”
Figure 10. Typical Device Power Consumption vs fmax
I CC can be estimated for the ispLSI 5128VE using the following equation:
High Speed Mode: ICC = 12.4 + (# of PTs * 0.408) + (# of nets * Fmax * 0.00169)
Low Power Mode: ICC = 12.4 + (# of PTs * 0.349) + (# of nets * Fmax * 0.00169)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Fmax = Highest Clock Frequency to the device
The I CC estimate is based on typical conditions (V CC = 3.3V, room temperature) and an assumption of one GLB load
on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions
and the program in the device, the actual I CC should be verified.
Power Consumption
180
165
150
135
120
105
90
0
25
Notes: Configuration of 8 16-bit Counters
50
Typical Current at 3.3V, 25° C
75
f
max (MHz)
100
18
setting operates product terms at their normal full power
consumption. For portions of the logic that can tolerate
longer propagation delays, selecting the slower “low-
power” setting will reduce the power dissipation for these
product terms. Figure 10 shows the relationship between
power and operating frequency.
Specifications ispLSI 5128VE
ispLSI 5128VE
Low Power Mode
125
ispLSI 5128VE
High Speed Mode
150
175
200
0127/5128VE