ISPLSI5128VE LATTICE [Lattice Semiconductor], ISPLSI5128VE Datasheet - Page 19

• Manufacturer Part Number: ISPLSI5128VE
• Description: In-System Programmable 3.3V SuperWIDE High Density PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

Signal Descriptions
TMS
TCK
TDI
TDO
TOE / I/O0
GOE0, GOE1
RESET
I/O
GND
VCC
CLK0, CLK1
CLK2 / I/O,
CLK3 / I/O
VCCIO
Signal Name
Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine.
Input - This pin is the Test Clock input pin used to clock through the JTAG state machine.
Input - This pin is the JTAG Test Data In pin used to load data.
Output - This pin is the JTAG Test Data Out pin used to shift data out.
Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon
customer's design. TOE tristates all I/O pins when a logic low is driven.
Input - These two pins are the Global Output Enable input pins.
Dedicated Reset Input - This pin resets all registers in the device. The global polarity (active
high or low input) for this pin is selectable.
Input/Output – These are the general purpose I/O used by the logic array.
Ground
Vcc
Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock
input to all registers in the device.
Input/Output - These pins share functionality. They can be used as dedicated clock inputs for
all registers, as well as I/O pins.
Input - This pin is used for optional 2.5V outputs. Every I/O can independently select either 3.3V
or the optional voltage as its output level. If the optional output voltage is not required, this pin
must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches
only draw current from this supply.
19
Description
Specifications ispLSI 5128VE