A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet - Page 32

• Manufacturer Part Number: A54SX16-1CG256
• Description: SX Family FPGAs RadTolerant and HiRel
• Manufacturer: ACTEL [Actel Corporation]

Pin Description
CLKA/B
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL,
LVTTL, 3.3 V PCI, or 5.0 V PCI specifications. The clock
input is buffered prior to clocking the R-cells. If not used,
this pin must be set LOW or HIGH on the board. It must
not be left floating. (For RT54SX72S, these clocks can be
configured as user I/O.)
GND
LOW supply voltage.
HCLK
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL, LVTTL, 3.3 V PCI
or 5.0 V PCI specifications. This input is directly wired to
each R-cell and offers clock speeds independent of the
number of R-cells being driven. If not used, this pin must
be set LOW or HIGH on the board. It must not be left
floating.
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard TTL,
LVTTL, 3.3 V PCI, or 5.0 V PCI specifications. Unused I/O
pins are automatically tristated by the Designer software.
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O,
The Probe pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the other
probe pin to allow real-time diagnostic output of any
signal path within the device. The Probe pin can be used
as a user-defined I/O when verification has been
completed.
permanently disabled to protect programmed design
confidentiality.
TCK, I/O
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (see
This pin functions as an I/O when the JTAG state machine
reaches the "logic reset" state.
1 -2 8
SX Family FPGAs RadTolerant and HiRel
The
Clock A and B
Ground
Dedicated (Hardwired) Array Clock
Input/Output
No Connection
Probe A/B PRB, I/O
Test Clock (Input)
pin’s
probe
Table 1-2 on page
capabilities
can
1-8).
be
v2.1
TDI, I/O
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set LOW (refer to
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDO, I/O
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 1-2 on page
the boundary scan state machine reaches the “logic
reset” state.
TMS
The TMS pin controls the use of the IEEE 1149.1
boundary scan pins (TCK, TDI, TDO, TRST). In flexible
mode, when the TMS pin is set LOW, the TCK, TDI, and
TDO pins are boundary scan pins (refer to
page
they will remain in that mode until the internal
boundary scan state machine reaches the "logic reset"
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The "logic
reset" state is reached five TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
TRST, I/O
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the Reserve JTAG Reset Pin
check box is cleared in Designer.
V
Supply voltage for I/Os. See
V
Supply voltage for Array. See
V
Supply voltage for input tolerance (required for internal
biasing). See
CCI
CCA
CCR
1-8). Once the boundary scan pins are in test mode,
Table 1-1 on page
Test Data Input
Test Data Output
Test Mode Select
Boundary Scan Reset Pin
Supply Voltage
Supply Voltage
Supply Voltage
1-8). This pin functions as an I/O when
Table 1-2 on page
Table 1-1 on page
Table 1-1 on page
1-8.
1-8). This pin
Table 1-2 on
1-8.
1-8.