A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet - Page 12

• Manufacturer Part Number: A54SX16-1CG256
• Description: SX Family FPGAs RadTolerant and HiRel
• Manufacturer: ACTEL [Actel Corporation]

Other Architecture
Performance
The combination of architectural features described
above enables RT54SX devices to operate with internal
clock frequencies exceeding 160 MHz, enabling very fast
execution of complex logic functions. Thus, the RTSX
family is an optimal platform upon which to integrate
the functionality previously contained in multiple CPLDs.
In addition, designs that previously would have required
a gate array to meet performance goals can now be
integrated
improvements in cost and time-to-market. Using timing-
driven place-and-route tools, designers can achieve
highly deterministic device performance. With RTSX
devices,
performance-enhancing
redundant logic to reduce fanout on critical nets, or the
instantiation of macros in HDL code to achieve high
performance.
I/O Modules
Each I/O on an RTSX device can be configured as an input,
an output, a tristate output, or a bidirectional pin. Even
without the inclusion of dedicated registers, these I/Os, in
combination with array registers, can achieve clock-to-out
(PAD-to-PAD) timing as fast as 5.8 ns. I/O cells including
embedded latches and flip-flops require instantiation in
HDL code. This is a design complication not encountered
in RTSX FPGAs. Fast PAD-to-PAD timing ensures that the
device will have little trouble interfacing with any other
device in the system, which in turn enables parallel design
of system components and reduces overall design time.
1 -8
SX Family FPGAs RadTolerant and HiRel
there
into
is
an
no
RTSX
design
need
device
to
techniques
use
with
complicated
dramatic
such
as
v2.1
Power Requirements
The RTSX family supports either 3.3 V or 5.0 V I/O voltage
operation and is designed to tolerate 5 V inputs in each
case
due to the very short distances signals are required to
travel to complete a circuit. Power requirements are
further reduced due to the small number of antifuses in
the path, and because of the low resistance properties of
the antifuses. The antifuse architecture does not require
active circuitry to hold a charge (as do SRAM or EPROM),
making it the lowest-power architecture on the market.
Table 1-1 • Supply Voltages
Boundary Scan Testing (BST)
All RTSX devices are IEEE 1149.1 (JTAG) compliant. They
offer superior diagnostic and testing capabilities by
providing BST and probing capabilities. These functions
are controlled through the special test pins in conjunction
with the program fuse. The functionality of each pin is
described in
diagram of the RTSX JTAG circuitry.
Table 1-2 • Boundary Scan Pin Functionality
A54SX16
A54SX32
RTSX16
RTSX32
Program Fuse Blown
(Dedicated Test Mode)
TCK, TDI, TDO are dedicated
test pins
No need for pull-up resistor for
TMS
(Table
1-1). Power consumption is extremely low
V
3.3 V
3.3 V
Table
CCA
1-2.
3.3 V
3.3 V
V
CCI
Figure 1-10 on page 1-9
V
5.0 V
5.0 V
CCR
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are flexible and
may be used as I/Os
Use a pull-up resistor of
10 kΩ on TMS
Maximum
Tolerance
Input
5.0 V
5.0 V
Maximum
Output
is a block
Drive
3.3 V
3.3 V