A54SX16-1CG256 ACTEL [Actel Corporation], A54SX16-1CG256 Datasheet - Page 20

• Manufacturer Part Number: A54SX16-1CG256
• Description: SX Family FPGAs RadTolerant and HiRel
• Manufacturer: ACTEL [Actel Corporation]

C
To calculate the active power dissipated by the complete
design, the switching frequency of each part of the logic
must be known.
summation over all components.
where:
1 -1 6
m
n
p
q
q
r
r
s
C
C
C
C
C
C
f
f
f
f
f
1
2
1
m
n
p
q1
q2
EQ
1
2
EQM
EQI
EQO
EQCR
EQCD
L
SX Family FPGAs RadTolerant and HiRel
Power = V
(n * C
0.5 * (q
0.5 * (q
0.5 * (s
Values (pF)
= Number of logic modules switching at f
= Number of input buffers switching at f
= Number of output buffers switching at f
= Number of clock loads on the first routed
= Number of clock loads on the second routed
= Fixed capacitance due to first routed array
= Fixed capacitance due to second routed
= Fixed number of clock loads on the
= Equivalent capacitance of logic modules in
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in
= Equivalent capacitance of routed array clock
= Equivalent capacitance of dedicated array
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in
EQI
1
1
2
* C
array clock
array clock
clock
array clock
dedicated array clock (528 for A54SX16)
pF
pF
in pF
clock in pF
MHz
* f
* C
* C
CCA
n
EQCD
EQCR
EQCR
)
inputs
2
* [(m * C
* f
* f
* f
EQ 1-4
+ (p * (C
s1
q1
q2
)
)
)
dedicated_CLK
routed_Clk1
routed_Clk2
EQM
EQO
shows a piecewise linear
* f
+ C
m
+ (r
)
+ (r
modules
]
L
) * f
2
1
* f
* f
p
)
q2
outputs
+
q1
)
)
routed_Clk2
routed_Clk1
+
n
EQ 1-4
m
p
+
+
v2.1
Determining Average Switching
Frequency
To determine the switching frequency for a design, you
must have a detailed understanding of the data input
values to the circuit. The following guidelines are meant
to represent worst-case scenarios so they can be
generally used to predict the upper limits of power
dissipation.
Logic Modules (m)
Inputs Switching (n)
Outputs Switching (p)
First Routed Array Clock Loads (q
Second Routed Array Clock Loads
(q
Load Capacitance (C
Average Logic Module Switching
Rate (f
Average Input Switching Rate (f
Average Output Switching Rate (f
Average First Routed Array Clock
Rate (f
Average Second Routed Array
Clock Rate (f
Average Dedicated Array Clock
Rate (f
2
)
m
q1
s1
)
)
)
q2
)
L
)
n
1
)
) =
p
) =
=
=
=
=
=
=
=
=
=
=
80% of modules
# inputs/4
# output/4
40% of sequential
modules
40% of sequential
modules
35 pF
F/10
F/5
F/10
F/2
F/2
F