AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 242

• Manufacturer Part Number: AGL015
• Description: IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
• Manufacturer: MICROSEMI [Microsemi Corporation]

Datasheet Information
5- 6
Revision / Version
Revision 8 (cont’d)
Revision 7 (Jun 2008)
Packaging v1.5
Revision 6 (Jun 2008)
Packaging v1.4
Revision 5 (Mar 2008)
Packaging v1.3
Revision 4 (Mar 2008)
Product Brief v1.0
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings,
Software
Default I/O Software
Power (per pin) – Default I/O Software Settings
to PDC6 and PDC3 to PDC7. The table notes were updated to reflect that power
was measured on VCCI.
In
Consumption in IGLOO
Static to Dynamic.
Table 2-20 • Different Components Contributing to the Static Power Consumption
in IGLOO Devices
Static Power Consumption in IGLOO Device
PDC7, and to change the definition for PDC5 to bank quiescent power. Subtitles
were added to indicate type of devices and core supply voltage.
The
calculation of P
Footnote †
Contribution equation was changed from: P
P
The
1 was changed from top view to bottom view, and note 2 is new.
This document was divided into two sections and given a version number, starting
at v1.0. The first section of the document includes features, benefits, ordering
information, and temperature and speed grade offerings. The second section is a
device family overview.
Pin numbers were added to the
below the diagram.
The
The
to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 µW)" was removed
from "Low Power Active FPGA Operation."
1.2_V was added to the list of core and I/O voltages in the
"I/Os with Advanced I/O Standards" section
The
from the section heading and place it instead after "4,608-Bit" and "True Dual-
Port SRAM (except ×18)."
PLL
Table 2-19 • Different Components Contributing to Dynamic Power
"QN132"
"CS196"
"Low Power" section
"Embedded Memory" section
"Total Static Power Consumption—P
= P
DC4
Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O
Settings,
was updated to include information about PAC13. The PLL
+ P
package and pin table was added for AGL250.
package diagram was updated to include D1 to D4. In addition, note
STAT
AC13
Table 2-15 • Summary of I/O Input Buffer Power (per pin) –
, including PDC6 and PDC7.
and
* F
Changes (prior versioning system)
Settings, and
CLKOUT
Table 2-22 • Different Components Contributing to the
Devices, the description for PAC13 was changed from
was updated to change "1.2 V and 1.5 V Core Voltage"
.
R ev isio n 1 9
"QN68"
was updated to remove the footnote reference
Table 2-16 • Summary of I/O Output Buffer
STAT
package diagram. Note 2 was added
sections.
PLL
" section
were updated to add PDC6 and
1
= P
were updated to change PDC2
AC13
was updated to revise the
+ P
"Advanced I/O"
AC14
* F
CLKOUT
and
to
through
2-14,
Page
I,
2-10
2-13
2-16
2-17
2-18
4-30
4-27
4-14
2-11
N/A
1-7
I
I