AGL015 MICROSEMI [Microsemi Corporation], AGL015 Datasheet - Page 151

• Manufacturer Part Number: AGL015
• Description: IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
• Manufacturer: MICROSEMI [Microsemi Corporation]

When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering
Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.
The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in
which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
Table 3-1
Flash*Freeze pin location is independent of device, allowing migration to larger or smaller IGLOO
devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology
and Low Power Modes" chapter of the
states during Flash*Freeze mode.
Table 3-1 • Flash*Freeze Pin Location in IGLOO Family Packages (device-independent)
IGLOO Packages
CS81/UC81
CS121
CS196
CS281
QN48
QN68
QN132
VQ100
FG144
FG256
FG484
shows the Flash*Freeze pin location on the available packages for IGLOO a devices. The
IGLOO FPGA Fabric User’s Guide
R ev i si o n 1 9
IGLOO Low Power Flash FPGAs
for more information on I/O
Flash*Freeze Pin
B12
W2
W6
H2
P3
14
18
27
L3
T3
J5
3 -3