ISPPACCLK5610AV-01T100C LATTICE [Lattice Semiconductor], ISPPACCLK5610AV-01T100C Datasheet - Page 51

• Manufacturer Part Number: ISPPACCLK5610AV-01T100C
• Description: In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Revision History
March 2007
June 2008
Date
—
Version
01.3
01.4
—
Previous Lattice releases.
Added min. and max. values to Timing Adders for I/O Modes table.
Added min. and max. values to PLL Bypass Mode operation table.
Added Phase Lock Detect feature description.
Added M-Divider and N-Divider Bypass feature description.
Modified logic standard related timing adder values in the Output Skew Matching Accu-
racy section and the Static Phase Offset and I/O Skew section.
PFD frequency limitation for the Static Phase Offset specification is removed.
Minimum operating voltage for V
Updated the I
Restructured / reordered sections under "Detailed Description" and "Thermal Manage-
ment"
Added a paragraph describing RESET in the "M-Divider and N-Divider Bypass Mode" sec-
tion.
Clairified the need for resetting ispClock in the “RESET and Power-up Functions” section.
CCD
vs. F
VCO
1-51
graph to include 800 MHz VCO frequency operation.
CCJ
Change Summary
is set to 2.25V.
ispClock5600A Family Data Sheet