ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 21

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Differential HSTL and SSTL
HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory
systems. Figure 16 shows how ispClock5600 reference input should be configured for accepting these standards.
The major difference between differential and single-ended forms of these logic standards is that in the differential
case, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are
engaged and set to 50Ω.
Figure 16. Differential HSTL/SSTL Receiver Configuration
LVDS/Differential LVPECL
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50Ω. The associated REFVTT or FBKVTT pin, however, should be left unconnected. This cre-
ates a floating 100Ω differential termination resistance across the input terminals. The LVDS termination configura-
tion is shown in Figure 17.
Figure 17. LVDS Input Receiver Configuration
Driver
LVDS
VTT
+Signal In
-Signal In
REFVTT
REFA+
REFA-
-Signal In
+Signal In
ispClock5600
50
CLOSED
No Connect
REFVTT
50
REFA+
REFA-
21
CLOSED
ispClock5600
50
Differential
Receiver
CLOSED
ispClock5600 Family Data Sheet
50
CLOSED
Differential
Receiver