ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 18

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 3. Nominal Output Duty Cycle vs. V-Divider Setting
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the output of the M divider
is routed directly to the inputs of the V dividers. In PLL_BYPASS mode, the nominal values of the V dividers are
halved, so that they provide division ratios ranging from 1 to 32. The output frequency for a given V divider (f
be determined by
Please note that PLL_BYPASS mode is provided primarily for testing purposes. When PLL_BYPASS mode is
enabled, features such as lock detect and skew generation are unavailable.
Reference and External Feedback Inputs
The ispClock5600 provide sets of configurable, internally-terminated inputs for both clock reference and feedback
signals. In normal operation, the one of the clock reference input pairs (REFA+/- or REFB+/-) is used as a clock
input.
The external feedback inputs make it possible to sample an output signal at the point of delivery. This makes it pos-
sible to provide output clocks which have very low skews in relation to the reference clock regardless of loading
effects.
The ispClock5610 provides one input signal pair for reference input and one input pair for external feedback, while
the ispClock5620 provides two pairs for reference signals and two pairs for feedback. To select between reference
and feedback inputs, the ispClock5620 provides two CMOS-compatible digital inputs called REFSEL and FBKSEL.
Table 4 shows the behavior of these two control inputs.
with 50% Output
Divider Settings
12
16
20
24
28
32
36
40
44
48
52
56
60
64
V
2
4
8
Duty Cycle
DC%
50
f
k
=
18
f
M x V
ref
x 2
Non-50% Output Duty
Divider Settings with
k
10
14
18
22
26
30
34
38
42
46
50
54
58
62
V
6
Cycles
ispClock5600 Family Data Sheet
DC%
33
40
43
44
45
46
47
47
47
48
48
48
48
48
48
k
) will
(2)