WM8985_07 WOLFSON [Wolfson Microelectronics plc], WM8985_07 Datasheet - Page 79

• Manufacturer Part Number: WM8985_07
• Description: Multimedia CODEC With Class D Headphone and Line Out
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

Pre-Production
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
Figure 38 PLL and Clock Select Circuit
w
The PLL can be enabled or disabled by the PLLEN register bit.
Table 46 PLLEN Control Bit
EXAMPLE:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a
selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
The WM8985 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8985 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from
an existing audio master clock.
Figure shows the PLL and internal clocking on the WM8985.
The PLL frequency ratio R = f
R1 (01h)
Power
management 1
REGISTER
ADDRESS
PLLN = int R
PLLK = int (2
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 2
24
x (8.192 – 8)) = 3221225 = 3126E9h
5
24
BIT
(R-PLLN))
2
/f
PLLEN
LABEL
1
(see Figure ) can be set using the register bits PLLK and PLLN:
2
0
DEFAULT
= 4 x 2 x 12.288MHz = 98.304MHz.
PLL enable
0 = PLL off
1 = PLL on
DESCRIPTION
PP, Rev 3.5, January 2007
WM8985
79