WM8753LEB/RV WOLFSON [Wolfson Microelectronics plc], WM8753LEB/RV Datasheet - Page 13

• Manufacturer Part Number: WM8753LEB/RV
• Description: HI FI AND TELEPHONY DUAL CODEC
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8753L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MODE/GPIO3 AND CSB/GPIO5 LATCH ON POWERUP TIMING
w
Test Conditions
CLKDIV2=0, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, T
Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock cycle time
MCLK duty cycle
Test Conditions
CLKDIV2=1, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, T
Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
Figure 1 System Clock Timing Requirements
MCLK
Power-on-Reset
AVDD/DCVDD
MODE/GPIO3
CSB/GPIO5
(internal)
DBVDD
t
pusetup
t
SYMBOL
SYMBOL
T
dbpu
T
T
T
T
MCLKDS
MCLKY
MCLKH
MCLKY
MCLKL
t
t
MCLKL
puhold
t
MCLKY
t
MCLKH
60:40
54
10
10
27
MIN
MIN
TYP
TYP
AI Rev 3.1 June 2004
Advanced Information
40:60
MAX
MAX
A
A
= +25
= +25
UNIT
UNIT
ns
ns
ns
ns
o
o
C,
C,
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