WM8973_05 WOLFSON [Wolfson Microelectronics plc], WM8973_05 Datasheet - Page 50

• Manufacturer Part Number: WM8973_05
• Description: Stereo CODEC for Portable Audio Applications
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM8973L
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STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8973L, the master clock may be
stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In
Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.
However, since setting DIGENB has no effect on the power consumption of other system
components external to the WM8973L, it is preferable to disable the master clock at its source
wherever possible.
Table 44 ADC and DAC Oversampling Rate Selection
NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set
to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may
prevent DACs and ADCs from re-starting correctly.
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 128x oversampling mode.
Under the control of ADCOSR and DACOSR the oversampling rate may be halved. This will result in
a slight decrease in noise performance but will also reduce the power consumption of the device. In
USB mode ADCOSR must be set to 0, i.e. 128x oversampling.
Table 45 ADC and DAC Oversampling Rate Selection
ADCOSR set to ‘1’, 64x oversample mode, is not supported in USB mode (USB=1).
SAVING POWER AT HIGHER SUPPLY VOLTAGES
The analogue supplies to the WM8973L can run from 1.8V to 3.6V. By default, all analogue circuitry
on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down
to 1.8V. At lower voltages, performance can be improved by increasing the bias current. If low
power operation is preferred the bias current can be left at the default setting. This is controlled as
shown below.
R25 (19h)
Additional Control
(1)
R24 (18h)
Additional Control
(2)
R23 (17h)
Additional
Control(1)
REGISTER
ADDRESS
REGISTER
REGISTER
ADDRESS
ADDRESS
7:6
BIT
0
1
0
VSEL
[1:0]
LABEL
BIT
BIT
DIGENB
ADCOSR
DACOSR
11
DEFAULT
LABEL
LABEL
0
0
0
Analogue Bias optimization
00: Highest bias current, optimized for
AVDD=1.8V
01: Bias current optimized for AVDD=2.5V
1X: Lowest bias current, optimized for AVDD=3.3V
DEFAULT
DEFAULT
DESCRIPTION
Master clock disable
0: master clock enabled
1: master clock disabled
ADC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
DAC oversample rate select
1 = 64x (lowest power)
0 = 128x (best SNR)
PD Rev 4.2 September 2005
DESCRIPTION
DESCRIPTION
Production Data
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