73S8014RT TERIDIAN [Teridian Semiconductor Corporation], 73S8014RT Datasheet - Page 17

• Manufacturer Part Number: 73S8014RT
• Description: Smart Card Interface
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

Using 1% external resistors and a parallel resistance of 24K ohms will result in a +/- 6% tolerance in the value of
VDD Fault. The sources of variation due to integrated circuit process variations and mismatches include the
internal reference voltage (less than +/- 1%), the internal comparator hysteresis and offset (less than +/- 1.7% for
part-to-part, processing and environment), the internal resistor value mismatch and value variations (less than
1.8%), and the external resistor values (1%).
If the 2.26V default threshold is used, this pin must be left unconnected.
3.4 Card Power Supply
The card power supply is internally provided by the LDO regulator and controlled by the digital ISO-7816-3
sequencer. Card voltage selection on the 73S8014RT is carried out by the digital inputs CMDVCC% and
CMDVCC#.
3.5 On-Chip Oscillator and Card Clock
The 73S8014RT devices have an on-chip oscillator that can generate the smart card clock using an external
crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock
signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be
left unconnected.
The card clock frequency may be chosen between 4 different division rates, defined by digital inputs CLKDIV 1
and CLKDIV 2, as per the following table:
3.6 Activation Sequence
The 73S8014RT smart card interface ICs have an internal 10ms delay on the application of V
V
must then be set low to activate the card. In order to initiate activation, the card must be present; there can be no
V
The following steps show the activation sequence and the timing of the card control signals when the system
controller sets CMDVCC% or CMDVCC# low while the RSTIN is low:
Rev. 1.0
DDF
DD
-
-
-
-
-
fault.
. No activation is allowed during this 10ms period. The CMDVCC% or CMDVCC# (edge triggered) signals
CMDVCC% or CMDVCC# is set low at t
V
the end of t
at t
Turn I/O to reception mode at t
CLK is applied to the card at t
RST is a copy of RSTIN after t
CC
1
, the OFF goes low to report a fault to the system controller, and V
will rise to the selected level and then the internal V
1
. In normal operation, the voltage V
CLKDIV1
0
0
1
1
3
3
.
CLKDIV2
2
.
.
0
1
0
1
0
.
1/6
¼ XTALIN
½ XTALIN
XTALIN
CC
CLK
XTALIN
to the card becomes valid before t
CC
control circuit checks the presence of V
Max XTALIN
27MHz
27MHz
20MHz
27MHz
CC
to the card is shut off.
1
DD
. If V
where V
CC
is not valid
DD
CC
>
at
17