PT7A4410J ETC1 [List of Unclassifed Manufacturers], PT7A4410J Datasheet - Page 32
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PT7A4410J
Manufacturer Part Number
PT7A4410J
Description
T1/E1/OC3 System Synchronizer
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.PT7A4410J.pdf
(34 pages)
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Test Conditions:
1. PRI reference input selected.
2. SEC reference input selected.
3. Normal State selected.
4. Holdover State selected.
5. Free-Run State selected.
6. 8kHz frequency source selected.
7. 1.544MHz frequency source selected.
8. 2.048MHz frequency source selected.
9. Master clock input OSCi at 20MHz ±0ppm.
10. Master clock input OSCi at 20MHz ±32ppm.
11. Master clock input OSCi at 20MHz ±100ppm.
12. Selected reference input at ±0ppm.
13. Selected reference input at ±32ppm.
14. Selected reference input at ±100ppm.
15. For Free-Run State of ±0ppm.
16. For Free-Run State of ±32ppm.
17. For Free-Run State of ±100ppm.
18. For capture range of ±230ppm.
19. For capture range of ±198ppm.
20. For capture range of ±130ppm.
21. 25pF capacitive load.
PT0106(09/02)
Notes:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Supply voltage and operation temperature are as per Recommended Operating Conditions.
3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter Measurement.
32
22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI
23. Jitter on reference input is less than 7ns p-p.
24. Applied jitter is sinusoidal.
25. Minimum applied input jitter magnitude to regain syn-
26. Loss of synchronization is obtained at slightly higher in-
27. Within 10ms of the state, reference or input change.
28. 1UIpp = 125 s for 8kHz signals.
29. 1UIpp = 648ns for 1.544MHz signals.
30. 1UIpp = 488ns for 2.048MHz signals.
31. 1UIpp = 324ns for 3.088MHz signals.
32. 1UIpp = 244ns for 4.096MHz signals.
33. 1UIpp = 122ns for 8.192MHz signals.
34. 1UIpp = 61ns for 16.384MHz signals.
35. No filter.
36. 40Hz to 100kHz bandpass filter.
37. With respect to reference input signal frequency.
38. After a RST or TCLR.
39. Master clock duty cycle 40% to 60%.
40. Prior to Holdover State, device was in Normal State and
41. 1UIpp = 162ns for 6.312MHz signals.
42. 1UIpp = 51ns for 19.44MHz signals.
p-p where 1UI p-p = 1/20MHz.
chronization.
phase locked.
put jitter amplitudes.
T1/E1/OC3 System Synchronizer
PT7A4410/4410L
Data Sheet
Ver:0