PT7A4410J ETC1 [List of Unclassifed Manufacturers], PT7A4410J Datasheet - Page 10

• Manufacturer Part Number: PT7A4410J
• Description: T1/E1/OC3 System Synchronizer
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

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Mode/State Control Machine
The Mode/State Control Machine determines whether the
PT7A4410/4410L operates in Automatic or Manual mode, and
whether it is in the Normal, Holdover or Free-Run state. In
Automatic Mode, the PT7A4410/4410L selects one of three
states, Normal, Holdover or Free-Run State. The sequence is
determined by LOS1, LOS2 and GTi signals. In Manual Mode,
a single state of operation is selected, in accordance with the
MS1, MS2, GTi and RSEL signals.
All mode and state changes are synchronous with the rising
edge of F8. See the Modes and States of Operation section for
complete details.
Guard Time Circuit
The Guard Time Circuit sends control signal (GTi) to Mode/
State Control Machine for control of Modes and States. It has
two functions:
Under Automatic Mode and in Primary Normal State, two state
changes are possible (not counting Auto-Holdover). They are:
The level at the GTi pin determines which state occurs. When
Input Impairment Monitor
This circuit monitors the input signals to the DPLL and auto-
matically enables the Holdover State (Auto-Holdover) when
the incoming signal is completely lost, or if its frequency is
outside the auto-holdover capture range (either a small or large
amount). When the incoming signal returns to normal, the
DPLL will be returned to Normal State.
PT0106(09/02)
Figure 6. Block Diagram of Mode/State Control Machine
- Primary Normal to Primary Holdover, and
- Primary Normal to Secondary Normal.
- GTi=0, Primary Normal to Primary Holdover,
- GTi=1, Primary Normal to Secondary Normal.
- enabling/disabling the TIE Corrector (Manual and Au-
- selecting which mode change takes place (Automatic
RSEL
LOS2
LOS1
only).
tomatic) (Refer to Table 6 and 7);
To Reference
Select MUX
MS1
Control Machine
To Tie Corrector
Mode/State
MS2
Enable
HOLDOVER
State Select
To DPLL
To and From
Guard Time
Circuit
10
The Auto-Holdover circuit does not use TIE correction. There-
fore, the phase delay between the input and output after switch-
ing back to Normal State is preserved (is the same as just prior
to the switch to Auto-Holdover).
APLL
The analog PLL is intended to be used to achieve a 50% Duty
cycle output clock. Connecting C19 to ACKi will generate a
phase locked 19.44 MHz ACKo output with a nominal 50%
duty cycle and a maximum peak-to-peak unfiltered jitter of
0.174 U.I. . The analog PLL has an intrinsic jitter of less than
0.01 U.I. In order to achieve this low jitter level separate pins
are provided to power (AVDD, AGND) the APLL.
Modes and States of Operation
The PT7A4410/4410L operates either in Manual mode or Au-
tomatic mode. Each mode has three possible operating states,
Normal, Holdover or Free-Run.
Shown in Table 4 and Table 5 are the mode and state selection
instructions, using pins MS1, MS2, and RSEL.
Table 4. Input Reference Selection
Table 5. Operation Modes and States
M 2
M 2
M 2
M 2
M
M
M
M
M
M
M
A
0
0
1
1
S
S
S
S
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T1/E1/OC3 System Synchronizer
M 1
M 1
M 1
M 1
M
0
0
R
R
R
R
R
1
1
S
S
S
S
S
S
S
S
S
S
1
0
0
1
1
E
E
E
E
E
L
L
L
L
L
M
M
M
M
M
M
M
M
A
M
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