71M6543GH MAXIM [Maxim Integrated Products], 71M6543GH Datasheet - Page 37

• Manufacturer Part Number: 71M6543GH
• Description: Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation
• Manufacturer: MAXIM [Maxim Integrated Products]

All supported operation modes use oversampling for the incoming bit stream when receiving data. Each
bit is sampled three times at the projected middle of the bit duration. This technique allows for deviations
of the received baud rate from nominal of up to 3.5%.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communication in multi-processor systems. In this case, the slave processors have bit
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
the slave’s address, it sets the 9
processors compare the received byte with their address. If there is a match, the addressed slave clears
SM20 or SM21 and receive the rest of the message. The rest of the slaves ignore the message. After
addressing the slave, the host outputs the rest of the message with the 9
serial port receive interrupts is generated.
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
and S1CON shown in
v1.2
S0CON[7]
S0CON[6]
S0CON[5]
S0CON[4]
Mode 0
Mode 1
Mode 2
Mode 3
Bit
bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B) registers
for transmit and RB81 (S1CON[2]) for receive operations.
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant 1.
8-bit serial modes with parity can be simulated by setting and reading the 9
The proper way to clear these flag bits is to write a byte mask consisting of all ones except
for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to
ignore ones written to them.
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag is cleared unintentionally.
SM0
SM1
SM20
REN0
N/A
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of f
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud rate
generator or timer 1)
Symbol
Table 19
Table 19: The S0CON (UART0) Register (SFR 0x98)
© 2008–2011 Teridian Semiconductor Corporation
th
and
The SM0 and SM1 bits set the UART0 mode:
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
UART 0
bit to 1, causing a serial port receive interrupt in all the slaves. The slave
Table 20,
Mode
0
1
2
3
Table 18: UART Modes
respectively, and the PCON register shown in
CKMPU
N/A
8-bit UART
9-bit UART
9-bit UART
Description
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
N/A
N/A
71M6543F/H and 71M6543G/GH Data Sheet
Function
SM0
0
0
1
1
th
bit set to 0, so no additional
UART 1
SM1
0
1
0
1
th
bit, using the control
Table
21.
37