71M6543GH MAXIM [Maxim Integrated Products], 71M6543GH Datasheet - Page 28

• Manufacturer Part Number: 71M6543GH
• Description: Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation
• Manufacturer: MAXIM [Maxim Integrated Products]

71M6543F/H and 71M6543G/GH Data Sheet
The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and
SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53
(see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details).
2.3.7 CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle.
samples taken during one multiplexer cycle with MUX_DIV[3:0] = 7 (I/O RAM 0x2100[7:4]).
The number of samples processed during one accumulation cycle is controlled by the I/O RAM register
SUM_SAMPS[12:0] (0x2107[4:0] and 0x2108[7:0]). The integration time for each energy output is:
For example, SUM_SAMPS[12:0] = 2184 establishes 2184 multiplexer cycles per accumulation cycle or
2184/2184.53 = 0.9998 seconds. After an accumulation cycle is completed, the XFER_BUSY interrupt
signals to the MPU that accumulated data are available. The slight difference between the nominal length
of the accumulation interval (1000 ms) and the actual length of 999.8 ms (0.025%) is accounted for in the
CE code and is of no practical consequence.
28
MUX_SYNC
CE CODE
WPULSE
CK32
SUM_SAMPS[12:0] / 2184.53, where 2184.53 is the sample rate in Hz
RST
S
1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.
2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next
low-going pulse begins.
3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.
4. All dimensions are in CK_FIR cycles (4.92MHz).
5. If PLS_INTERVAL=0, FIFO does not perform delay.
0
4*PLS_INTERVAL
S
1
S
2
S
150
3
S
4
S
© 2008–2011 Teridian Semiconductor Corporation
S
5
0
4*PLS_INTERVAL
Figure 9. Pulse Generator FIFO Timing
S
0
MUX_DIV
S
1
4*PLS_INTERVAL
Conversions (MUX_DIV=4 is shown)
S
1
ADC MUX Frame
S
W_FIFO
2
4*PLS_INTERVAL
S
2
Figure 10
S
3
4*PLS_INTERVAL
S
shows the timing of the
3
S
4
4*PLS_INTERVAL
S
4
Settle
S
5
v1.2
S
5