71M6543GH MAXIM [Maxim Integrated Products], 71M6543GH Datasheet - Page 36

• Manufacturer Part Number: 71M6543GH
• Description: Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation
• Manufacturer: MAXIM [Maxim Integrated Products]

71M6543F/H and 71M6543G/GH Data Sheet
The MPU core power consumption can be significantly reduced by the proper use of Idle Mode. The
amount of power saved depends on the percentage of time spent in Idle Mode. Since some interrupts
may occur frequently, thus ending Idle Mode, one method to maximize power savings using Idle Mode, is
to employ a software loop in the main background routine at a point where the MPU background
processing may be permitted to idle. This loop invokes Idle Mode while testing a bit to exit the loop.
Frequently occurring interrupts end Idle Mode, but Idle Mode is immediately re-entered when control is
returned to the idle loop. To exit the idle loop, an interrupt must occur, and the associated interrupt
service routine must set the bit that terminates the idle loop execution.
Power-Down Mode halts the MPU and its peripherals. Power-Down Mode is ended by either a hardware
reset or an external interrupt event. To enter Power-Down Mode, the firmware must set the PD bit (bit 1)
in the PCON SFR register (SFR 0x87).
2.4.6 UARTs
The 71M6543 include a UART (UART0) that can be programmed to communicate with a variety of AMR
modules and other external devices. A second UART (UART1) is connected to the optical port, as
described in the
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor
at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as
follows:
•
•
The 71M6543 has several UART-related registers for the control and buffering of serial data.
A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0
and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and
when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the
transmission by the associated UART. Received data are available by reading from the receive buffer.
Both UARTs can simultaneously transmit and receive data.
WDCON[7] (SFR 0xD8) selects whether timer 1 or the internal baud rate generator is used. All UART
transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for
variable communication baud rates from 300 to 38400 bps.
calculated.
S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.
(S0RELL, S0RELH, S1RELL, S1RELH are SFR 0xAA, SFR 0xBA, SFR 0x9D and SFR 0xBB, respectively) SMOD
is the SMOD bit in the SFR PCON register (SFR 0x87). TH1 (SFR 0x8D) is the high byte of timer 1.
36
UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.
UART0
UART1
Notes:
The SMOD bit is not related to power management.
See
Table 18
SMOD
Bit 7
2.4.6 UARTs
2.5.9 UART and Optical Interface
shows the selectable UART operation modes.
2
N/A
Bit 6
smod
-
© 2008–2011 Teridian Semiconductor Corporation
Table 16. 80515 PCON SFR Register (SFR 0x87)
* f
below for information on the SMOD bit.
CKMPU
(WDCON[7] = 0)
Using Timer 1
Bit 5
Table 17: Baud Rate Generation
-
/ (384 * (256-TH1))
Bit 4
-
on page 57.
Bit 3
-
2
f
Table 17
CKMPU
smod
Using Internal Baud Rate Generator
* f
/(32 * (2
Bit 2
CKMPU
-
shows how the baud rates are
/(64 * (2
10
(WDCON[7] = 1)
-S1REL))
Bit 1
PD
10
-S0REL))
Bit 0
IDL
v1.2