71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 45

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 35)
(SFR 0xB9)
sequence as shown in
Register
IP0
IP1
EX_WPULSE
EX_XPULSE
EX_YPULSE
EX_VPULSE
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
EX_EEX
EX_SPI
Name
Group
by setting or clearing one bit in the SFR interrupt priority register IP0 (SFR 0xA9) and one in IP1
Interrupt Enable
(Table
0
1
2
3
4
5
SFR 0xA9
SFR 0xB9
Address
36). If requests of the same priority level are received simultaneously, an internal polling
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
0x2701[7]
0x2700[7]
0x2700[6]
0x2700[5]
0x2701[6]
0x2701[5]
Location
Table 37
Table 36: Interrupt Priority Registers (IP0 and IP1)
(MSB)
Bit 7
Table 34: Interrupt Priority Level Groups
–
–
IP1[x]
determines which request is serviced first.
–
0
0
1
1
Table 35: Interrupt Priority Levels
IE_WPULSE
IE_XPULSE
IE_VPULSE
IE_YPULSE
IE_EEX
IE_SPI
Name
Bit 6
–
–
Interrupt Flag
IP0[x]
0
1
0
1
IP0[5]
IP1[5]
Serial channel 1 interrupt
Bit 5
Group Members
SFR 0xE8[7]
SFR 0xE8[6]
SFR 0xE8[5]
SFR 0xF8[7]
SFR 0xF8[4]
SFR 0xF8[3]
Location
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
Table
IP0[4]
IP1[4]
Bit 4
Priority Level
71M6541D/F/G and 71M6542F/G Data Sheet
–
–
–
–
–
34.
SPI interrupt
EEPROM interrupt
CE_XPULSE interrupt (int 2)
CE_YPULSE interrupt (int 2)
CE_WPULSE interrupt (int 2)
CE_VPULSE interrupt (int 2)
IP0[3]
IP1[3]
Bit 3
Interrupt Description
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
IP0[2]
IP1[2]
Bit 2
–
IP0[1]
IP1[1]
Bit 1
IP0[0]
IP1[0]
(LSB)
Bit 0