71M6542F MAXIM [Maxim Integrated Products], 71M6542F Datasheet - Page 33

• Manufacturer Part Number: 71M6542F
• Description: 0.1% Accuracy Over 2000:1 Current Range Energy Meter ICs
• Manufacturer: MAXIM [Maxim Integrated Products]

An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred
to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction
MOVX A,@Ri or MOVX @Ri,A.
Internal Data Memory Map and Access
The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory
address is always 1 byte wide.
The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory
is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of
Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32
bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW, SFR
0xD0 ) select which bank is in use. The next 16 bytes form a block of bit addressable memory space at
addresses 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect
addressing.
2.4.2 Special Function Registers (SFRs)
A map of the Special Function Registers is shown in
Only a few addresses in the SFR memory space are occupied, the others are not implemented. A read
access to unimplemented addresses returns undefined data, while a write access has no effect. SFRs
specific to the 71M654x are shown in bold print on a shaded field. The registers at 0x80, 0x88, 0x90,
etc., are bit addressable, all others are byte addressable.
Hex/
Bin
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
F8
F0
98
90
88
80
P3 (DIO12:15)
P2 (DIO8:11)
Addressable
P0 (DIO0:3)
Address Range
P1(DIO4:7)
0x80
0x30
0x20
0x00
INTBITS
IFLAGS
WDCON
T2CON
S0CON
IRCON
TCON
X000
IEN1
IEN0
PSW
Bit
B
A
0xFF
0x7F
0x2F
0x1F
VSTAT
S0BUF
TMOD
X001
IP1
IP0
SP
Special Function Registers (SFRs)
Table 12: Special Function Register Map
Table 11
FLSHCTL
Table 11: Internal Data Memory Map
S0RELH
S0RELL
X010
IEN2
DPL
DPS
TL0
Direct Addressing
shows the internal data memory map.
S1RELH
S1CON
X011
DPH
TL1
Register banks R0…R7
Byte Addressable
Byte addressable area
Bit addressable area
Table
ERASE
RCMD
S1BUF
DPL1
X100
TH0
12.
71M6541D/F/G and 71M6542F/G Data Sheet
SPI_CMD
S1RELL
DPH1
X101
TH1
Indirect Addressing
EEDATA EECTRL
CKCON
X110
RAM
FLSHPG
PDATA
PCON
X111
Bin/
Hex
DF
CF
BF
AF
EF
D7
C7
B7
A7
FF
F7
E7
9F
8F
97
87