71M6521DE TERIDIAN [Teridian Semiconductor Corporation], 71M6521DE Datasheet - Page 34

• Manufacturer Part Number: 71M6521DE
• Description: Energy Meter IC
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 48:
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the
special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 52 determines which request is serviced first.
An overview of the interrupt structure is given in Figure 6.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC,
which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 47)
and these interrupts must be cleared by the MPU software.
Interrupt Priority 0 Register (IP0)
Note: WDTS is not used for interrupt controls
Interrupt Priority 1 Register (IP1)
Page: 34 of 101
MSB
MSB
Group
0
1
2
3
4
5
--
-
Serial channel 0 interrupt
External interrupt 0
External interrupt 1
Timer 0 interrupt
Timer 1 interrupt
WDTS
-
© 2005-2008 TERIDIAN Semiconductor Corporation
IP1.x
-
0
0
1
1
IP0.5
IP1.5
Table 48: Priority Level Groups
Table 50: The IP1 Register:
Table 49: The IP0 Register
Table 51: Priority Levels
IP1.4
IP0.4
IP0.x
0
1
0
1
Serial channel 1 interrupt
IP0.3
IP1.3
Priority Level
Level0 (lowest)
Level1
Level2
Level3 (highest)
71M6521DE/71M6521FE
-
-
-
-
-
IP0.2
IP1.2
Energy Meter IC
IP0.1
IP1.1
External interrupt 2
External interrupt 4
External interrupt 6
External interrupt 3
External interrupt 5
LSB
LSB
IP0.0
IP1.0
DATASHEET
JANUARY 2008
v1.0