71M6511-IGT TERIDIAN [Teridian Semiconductor Corporation], 71M6511-IGT Datasheet - Page 33

• Manufacturer Part Number: 71M6511-IGT
• Description: Single-Phase Energy Meter IC
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 46:
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the
special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 50 determines which request is serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC,
which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 45),
and these interrupts must be cleared by the MPU software.
An overview of the interrupt structure is given in Figure 7.
Interrupt Priority 0 Register (IP0)
Interrupt Priority 1 Register (IP1)
Page: 33 of 95
MSB
MSB
Group
0
1
2
3
4
5
--
-
Serial channel 0 interrupt
External interrupt 0
External interrupt 1
WDTS
Timer 0 interrupt
Timer 1 interrupt
Note: WDTS is not used for interrupt controls
-
© 2005-2007 TERIDIAN Semiconductor Corporation
IP1.x
-
0
0
1
1
IP0.5
IP1.5
Table 46: Priority Level Groups
Table 47: The IP0 Register:
Table 48: The IP1 Register:
Table 49: Priority Levels
IP0.4
IP1.4
IP0.x
0
1
0
1
Serial channel 1 interrupt
IP0.3
IP1.3
Priority Level
Level0 (lowest)
Level1
Level2
Level3 (highest)
Single-Phase Energy Meter IC
-
-
-
-
-
IP0.2
IP1.2
71M6511/71M6511H
DATA SHEET
IP0.1
IP1.1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
LSB
LSB
IP0.0
IP1.0
AUGUST 2007
V2.6