LF3320QC15 LODEV [LOGIC Devices Incorporated], LF3320QC15 Datasheet - Page 8

• Manufacturer Part Number: LF3320QC15
• Description: Horizontal Digital Image Filter
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
28 clock cycles from the first data
input, DIN
first result is 11 clock cycles
(11+17 = 28). The result will appear at
the corresponding filter output,
DOUT
and single filter mode configurations,
the sum of products will continue to
appear every clock cycle thereafter
until the matrix dimension has been
realized. The total pipeline latency for
a complete [8x8][8x1] matrix-vector
operation is 26 clock cycles and the
total pipeline latency for a complete
[16x16][16x1] matrix-vector operation
is 43 clock cycles. Therefore, to process
two square matrices simultaneoulsy, of
size N=8, a total of 73 clock cycles are
all that is required. Similarly, to
process a single square matrix, of size
N=16, a total of 283 clock cycles are
required.
Once again, the timing diagrams (see
Figure 8 and 9) will assume that the
Configuration Registers, the coefficient
sets, and the data values have been
loaded. The corresponding timing
diagram loading sequence for the
coefficient banks and
Configuration/Control registers are
included in the LF3320 data sheets
F
IGURE
SHENA / SHENB
15-0
TXFRA/ TXFRB
CENA / CENB
9. S
. Subsequently, for both dual
15-0
DOUT
DIN
RIN
CAA
CAB
; device latency for the
INGLE
CLK
11-0
11-0
15-0
7-0
7-0
*
**
***
F
ILTER
11 Clocks - First Output of First Data/Coefficient Set
16 Clocks - End of First Data/Coefficient Set
26 Clocks - Final Output of First Data/Coefficient Set
CF
, M
1
00
ATRIX
DATA SET 0
CF
2
01
M
(Figure 11 and Figure 12 respectively).
Further reference to timing diagram
loading sequence for the RSL registers
are also included in the device data
sheet (Figure 15, Figure 14, and Figure
13). The Filter A and Filter B
LF Interface
into the Filter A and Filter B Configura-
tion Registers and coefficient banks.
The Matrix Multiplication Mode is
valid in the Double Wide
CF
ULTIPLY
3
F
02
IGURE
1 Data Set with 16 Coefficient Sets
T
DIN
RIN
10. D
IMING
11-0
11-0
TM
CF
11*
OUT 0
0A
are used to load data
12
12
S
OUBLE
CF
2-8
EQUENCE
12
OUT 1
0B
DATA SET 0
CF
W
REGISTERS
13
DOUT
OUT 2
0C
CIRCUIT
16
FILTER
R.S.L.
IDE
I/D
A
15-0
CF
14
D
OUT 3
0D
ATA
Horizontal Digital Image Filter
CF
15
/C
0E
OUT 4
OEFFICIENT
Data/Coefficient Mode. However,
there are some special considerations
when this mode is desired. The
LF3320 must be configured for single
filter mode only, for a maximum (8x8)
matrix. The user must disable the
cascaded filter mode, the accumulator
access mode, and the data reversal
(see Table 7).
Double Wide Data/Coefficient Mode
SCALE
CF
Video Imaging Products
16**
OUT 5
0F
CF
17
10
OUT 6
M
ODE
REGISTERS
FILTER
I/D
B
26***
OUT 15
08/16/2000–LDS.3320-N
LF3320