LF3320QC15 LODEV [LOGIC Devices Incorporated], LF3320QC15 Datasheet - Page 5

• Manufacturer Part Number: LF3320QC15
• Description: Horizontal Digital Image Filter
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
Registers on the rising edge of CLK.
When SHENB is HIGH, data can not be
loaded into the Cascade Registers or
shifted through the I/D Registers and
their contents will not be changed.
In Single Filter Mode, SHENB also
enables or disables the loading of data
into the Input (DIN
Cascade Output (ROUT
A I/D Registers. It is important to note
that in Single Filter Mode, both
SHENA and SHENB should be
connected together. Both must be
active to enable data loading in Single
Filter Mode. SHENB is latched on the
rising edge of CLK.
RSLA
RSLA
sixteen user-programmable Round/
Select/Limit registers (RSL registers)
are used in the Filter A RSL circuitry.
A value of 0 on RSLA
register 0. A value of 1 selects RSL
register 1 and so on. RSLA
latched on the rising edge of CLK (see
the round, select, and limit sections for
a complete discussion).
RSLB
RSLB
user-programmable RSL registers are
used in the Filter B RSL circuitry. A
value of 0 on RSLB
register 0. A value of 1 selects RSL
register 1 and so on. RSLB
on the rising edge of CLK (see the round,
select, and limit sections for a complete
discussion).
OED — DOUT Output Enable
When OED is LOW, DOUT
enabled for output. When OED is
HIGH, DOUT
impedance state.
OEC — COUT/ROUT Output Enable
When OEC is LOW, COUT
3-0
3-0
3-0
3-0
determines which of the sixteen
— Filter B Round/Select/Limit
— Filter A Round/Select/Limit
determines which of the
Control
Control
15-0
is placed in a high-
3-0
11-0
selects RSL
3-0
), Reverse
11-0
selects RSL
3-0
11-0
3-0
) and Filter
15-0
is latched
is
and
is
ROUT
OEC is HIGH, COUT
are placed in a high-impedance state.
PAUSEA — LF Interface
When PAUSEA is HIGH, the Filter A
LF Interface
halted until PAUSEA is returned to a
LOW state. This effectively allows the
user to load coefficients and control
registers at a slower rate than the
master clock (see the LF Interface
section for a full discussion).
F
F
ROUT
DIN
IGURE
IGURE
DIN
11-0
3-0
11-0
11-0
12
are enabled for output. When
4. S
5. D
12
12
TM
loading sequence is
INGLE
UAL
2-5
REGISTERS
DOUT
CIRCUIT
16
FILTER
REGISTERS
F
R.S.L.
11-0
I/D
A
FILTER
ILTER
F
TM
15-0
I/D
A
ILTER
and ROUT
Pause
M
M
ODE
TM
ODE
Horizontal Digital Image Filter
3-0
DOUT
CIRCUIT
16
RSL
15-0
PAUSEB — LF Interface
When PAUSEB is HIGH, the Filter B LF
Interface
until PAUSEB is returned to a LOW
state. This effectively allows the user
to load coefficients and control regis-
ters at a slower rate than the master
clock (see the LF Interface
a full discussion).
Video Imaging Products
ROUT
REGISTERS
TM
CIRCUIT
16
3-0
FILTER
R.S.L.
REGISTERS
I/D
B
/ COUT
loading sequence is halted
FILTER
I/D
B
11-0
TM
08/16/2000–LDS.3320-N
TM
Pause
12
12
LF3320
section for
12
RIN
COUT
RIN
11-0
11-0
11-0