X4285 XICOR [Xicor Inc.], X4285 Datasheet - Page 6

• Manufacturer Part Number: X4285
• Description: CPU Supervisor with 128K EEPROM
• Manufacturer: XICOR [Xicor Inc.]

X4283/85 – Preliminary Information
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4283/85 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and zeroes
to the other bits of the control register. Once set, WEL
remains set until either it is reset to 0 (by writing a “0” to
the WEL bit and zeroes to the other bits of the control
register) or until the part powers up again. Writes to the
WEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array.
REV 1.17 11/27/00
WPEN WD1 WD0 BP1 BP0
0
0
0
0
1
1
1
1
7
0
0
1
1
0
0
1
1
0
1
0
1 0000
0
1
0
1
6
Protected Addresses
3000
2000
000
000
000
None (factory setting)
000
h
h
h
h
h
h
h
5
- 3FFF
- 0FF
- 1FF
- 07F
- 3FFF
- 3FFF
- 03F
(Size)
h (128 bytes)
h (256 bytes)
h (512 bytes)
4
h (64 bytes)
h (16K bytes)
h (4K bytes
h (8K bytes
3
)
)
RWEL WEL BP2
Upper 1/2 (Q3,Q4)
2
First 2 pgs (P2)
First 4 pgs (P4)
First 8 pgs (P8)
Upper 1/4 (Q4)
First Page (P1)
Full Array (All)
Array Lock
None
1
www.xicor.com
0
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of eight blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit. Four of the 8 protected blocks
match the original Block Lock segments and this pro-
tection scheme is fully compatible with the current
devices using 2 bits of block lock control (assuming the
BP2 bit is set to 0).
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is Hard-
ware Write Protected, nonvolatile writes as well as to the
block protected sections in the memory array cannot be
written. Only the sections of the memory array that are
not block protected can be written. Note that since the
WPEN bit is write protected, it cannot be changed back
to a LOW state; so write protection is enabled as long
as the WP pin is held HIGH.
WD1
0
0
1
1
WD0
0
1
0
1
Characteristics subject to change without notice.
Watchdog Time Out Period
1.4 seconds (factory setting)
600 milliseconds
200 milliseconds
disabled
6 of 22