X4285 XICOR [Xicor Inc.], X4285 Datasheet - Page 11

• Manufacturer Part Number: X4285
• Description: CPU Supervisor with 128K EEPROM
• Manufacturer: XICOR [Xicor Inc.]

X4283/85 – Preliminary Information
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Figure 12. Current Address Read Sequence
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
Figure 13. Random Address Read Sequence
REV 1.17 11/27/00
Signals from
Signals from
the Master
the Slave
SDA Bus
S
a
r
t
t
1
0
Address
1
Slave
Signals from
Signals from
0
the Master
the Slave
SDA Bus
0
A
C
K
Word Address
S
a
Byte 1
t
r
t
1 0 1 0
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Address
Slave
A
C
K
Word Address
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 12 for
the
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
1
Byte 0
A
C
K
address,
Data
A
C
K
S
a
r
t
t
acknowledge,
Characteristics subject to change without notice.
Address
Slave
S
o
p
t
1
A
C
K
and
Data
data
transfer
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S
o
p
t