X4285 XICOR [Xicor Inc.], X4285 Datasheet - Page 3

• Manufacturer Part Number: X4285
• Description: CPU Supervisor with 128K EEPROM
• Manufacturer: XICOR [Xicor Inc.]

X4283/85 – Preliminary Information
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4283/85 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for 200ms (nominal) the circuit releases RESET/
RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4283/85 monitors the V
and asserts RESET/RESET if supply voltage falls
below a preset minimum V
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
V
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
Figure 1. Set V
REV 1.17 11/27/00
TRIP
SCL
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power up.
SDA
WP
for 200ms.
CC
exceeds the device V
0 1 2 3 4 5 6 7
TRIP
A0h
Level Sequence (V
TRIP
CC
. The RESET/RESET
returns and exceeds
TRIP
0 1 2 3 4 5 6 7
threshold value
CC
V
P
= 12-15V
00h
= desired V
CC
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level
TRIP
0 1 2 3 4 5 6 7
periodically, while SCL is HIGH (this is a start bit) prior
to the expiration of the watchdog time out period to pre-
vent a RESET/RESET signal. The state of two nonvola-
tile control bits in the Status Register determine the
watchdog timer period. The microprocessor can change
these watchdog bits, or they may be “locked” by tying
the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time-Out, any in-
progress
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Non-volatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
The X4283/85 is shipped with a standard V
old (V
mal operating and storage conditions. However, in
applications where the standard V
right, or if higher precision is needed in the V
value, the X4283/85 threshold may be adjusted. The
procedure is described below, and uses the application
of a nonvolatile control signal.
CC
values WEL bit set)
01h
THRESHOLD RESET PROCEDURE
TRIP
) voltage. This value will not change over nor-
communications
Characteristics subject to change without notice.
0 1 2 3 4 5 6 7
00h
are
terminated. While
TRIP
is not exactly
CC
thresh-
3 of 22
TRIP