ATA5771_09 ATMEL [ATMEL Corporation], ATA5771_09 Datasheet - Page 84

• Manufacturer Part Number: ATA5771_09
• Description: Microcontroller with UHF ASK/FSK Transmitter
• Manufacturer: ATMEL [ATMEL Corporation]

7.8
7.9
7.9.1
7701C–AVR–12/08
128 kHz Internal Oscillator
System Clock Prescaler
Switching Time
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25 C. This clock may be select as the system clock by
programming the CKSEL Fuses to “0100”.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 7-9 on page
Table 7-9.
The ATtiny24/44/84 system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.
SUT1..0
00
01
10
11
Start-up Time from Power-
Start-up Times for the 128 kHz Internal Oscillator
down and Power-save
31.
6 CK
6 CK
6 CK
Table 7-10 on page
Additional Delay from
Reserved
14CK + 64 ms
14CK + 4 ms
Reset
14CK
33.
I/O
, clk
ATtiny24/44/84
Fast rising power
BOD enabled
Slowly rising power
ADC
Recommended Usage
, clk
CPU
, and clk
FLASH
31