ATA5771_09 ATMEL [ATMEL Corporation], ATA5771_09 Datasheet - Page 65

• Manufacturer Part Number: ATA5771_09
• Description: Microcontroller with UHF ASK/FSK Transmitter
• Manufacturer: ATMEL [ATMEL Corporation]

5.7
5.8
12
Instruction Execution Timing
Reset and Interrupt Handling
ATtiny24/44/84
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 5-4 on page 12
by the Harvard architecture and the fast access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 5-4.
Figure 5-5 on page 12
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 5-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0.
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
Result Write Back
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
clk
clk
CPU
shows the parallel instruction fetches and instruction executions enabled
CPU
shows the internal timing concept for the Register File. In a single clock
CPU
T1
T1
, directly generated from the selected clock source for the
T2
T2
”Interrupts” on page
T3
T3
50. The list also
7701C–AVR–12/08
T4
T4