M40Z300MH1TR STMICROELECTRONICS [STMicroelectronics], M40Z300MH1TR Datasheet - Page 7

• Manufacturer Part Number: M40Z300MH1TR
• Description: 5V or 3V NVRAM Supervisor for Up to 8 LPSRAMs
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

OPERATION
The M40Z300/W, as shown in
can control up to four (eight, if placed in parallel)
standard low-power SRAMs. These SRAMs must
be configured to have the chip enable input dis-
able all other input signals. Most slow, low-power
SRAMs are configured like this, however many
fast SRAMs are not. During normal operating con-
ditions, the conditioned chip enable (E1
E4
pin with timing shown in
ble 7., page
to V
than 0.3V (I
When V
E1
of E. In this situation, the SRAM is unconditionally
write protected as V
ance threshold (V
er fail detection value associated with V
selected by the Threshold Select (THS) pin and is
shown in
the THS pin selects both the supply voltage and
V
Note: In either case, THS pin must be connected
to either V
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
Table 2. Truth Table
PFD
CON
CON
OUT
(also shown in
) output pins follow the chip enable (E) input
E
H
L
L
L
L
to E4
. This switch has a voltage drop of less
CC
Table 6., page
SS
OUT1
14. An internal switch connects V
CON
degrades during a power failure,
or V
).
OUT
PFD
are forced inactive independent
Inputs
CC
Table 6., page
). For the M40Z300 the pow-
.
B
X
H
H
L
L
falls below an out-of-toler-
Figure 8., page 8
12. For the M40Z300W,
Figure 7., page
12).
A
X
H
H
L
L
and
CON
PFD
WPT
Ta-
CC
6,
to
is
,
E1
H
H
H
H
CON
L
E1
write protecting the SRAM. A power failure during
a WRITE cycle may corrupt data at the currently
addressed location, but does not jeopardize the
rest of the SRAM's contents. At voltages below
V
will be write protected within the Write Protect
Time (t
(see
As V
disconnects V
to V
(V
age V
I
When V
back to the supply voltage. Outputs E1
E4
mum) after the power supply has reached V
independent of the E input, to allow for processor
stabilization (see
Two to Four Decode
The M40Z300/W includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in
OUT2
PFD
SO
Table 2.
CON
CON
OUT
). Below the V
Figure 8., page
CC
(min), the user can be assured the memory
(see
OHB
WPT
to E4
are held inactive for t
continues to degrade, the internal switch
. This occurs at the switchover voltage
CC
E2
) provided the V
Table 6., page
to the SRAM and can supply current
H
H
H
H
CON
L
rises above V
CON
CC
Outputs
and connects the internal battery
Figure 12., page
are unconditionally driven high,
SO
8).
, the battery provides a volt-
M40Z300, M40Z300W
E3
12).
H
H
H
H
CON
L
CC
SO
, V
fall time exceeds t
CER
OUT
13).
(120ms maxi-
is switched
E4
H
H
H
H
CON
L
CON
PFD
7/21
to
F
,