LMP8358MA NSC [National Semiconductor], LMP8358MA Datasheet - Page 19

• Manufacturer Part Number: LMP8358MA
• Description: Zero-Drift, Programmable Instrumentation Amplifier with Diagnostics
• Manufacturer: NSC [National Semiconductor]

Communication Mode Selection
The interface mode is determined by the two interface level
pins VLSER/VHPAR and VHSER/VLPAR.
VLSER/VHPAR < VHSER/
VLPAR
VLSER/VHPAR > VHSER/
VLPAR
The levels applied to the VLSER/VHPAR and VHSER/VL-
PAR pins should be between the V
in
PARALLEL CONTROL INTERFACE MODE
The LMP8358 is put into Parallel Mode by setting VLSER/
VHPAR > VHSER/VLPAR. The register in the LMP8358 does
not control the settings of the LMP8358 in this mode. Gain
and shutdown are set by placing a high or low logic level on
pins 11 (SHDN), 12 (G2), 13 (G1), and 14 (G0), as shown in
Table 1. Function of Digital IO Pins, Parallel Mode
2. Pin Levels for Setting Gain, Parallel
and low levels are defined by the voltages on the VLSER/
VHPAR and VHSER/VLPAR pins. See the
POWER ON RESET
using the parallel mode.
Figure
FIGURE 1. (A) Communication with LMP8358 in Parallel Mode (B) Communication with LMP8358 in Serial Mode
FIGURE 2. Communication Mode Selection.
2.
section for power on requirements when
Serial
Logic low level, VHSER =
Logic high level.
Parallel interface. VLPAR =
Logic low level, VHPAR =
Logic high level.
+
and V
Mode. The logic high
Interface.
−
START UP AND
levels as shown
30045409
and
VLSER=
Table
19
SERIAL CONTROL INTERFACE MODE
The LMP8358 is put into Serial Mode by setting VLSER/VH-
PAR < VHSER/VLPAR. In the Serial Mode the LMP8358 can
be programmed by using pins 11 – 14 as shown in
Function of Digital IO Pins, Serial Mode
Diagram. The LMP8358 contains a 16 bit register which con-
trols the performance of the part. These bits can be changed
using the Serial Mode of communication. The register of the
LMP8358 is shown in
tion, Serial
should be written with the value needed for the application.
See the
Pin Name
G0
G1
G2
SHDN
VHPAR
VLPAR
G2
0
0
0
0
1
1
1
1
Table 2. Pin Levels for Setting Gain, Parallel Mode
Table 1. Function of Digital IO Pins, Parallel Mode
G1 G0 Gain Setting
0
0
1
1
0
0
1
1
START UP AND POWER ON RESET
0
1
0
1
0
1
0
1
Mode. Immediately after power on the register
10x (power-up
default)
20x
50x
100x
200x
500x
1000x
User defined
Description
Gain setting (LSB)
Gain setting
Gain setting (MSB)
Shutdown (Active High)
Positive logic level
Negative logic level
Table 4. LMP8358 Register Descrip-
Bandwidth Compen-
930 kHz
385 kHz
460 kHz
640 kHz
195 kHz
130 kHz
89 kHz
800 kHz
and the SPI Timing
section.
300454a5
sation
Setting
(Auto-
matically
Set)
000b
000b
001b
010b
010b
011b
011b
1xxb
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Table 3.