S9S08AW16A FREESCALE [Freescale Semiconductor, Inc], S9S08AW16A Datasheet - Page 221

no-image

S9S08AW16A

Manufacturer Part Number
S9S08AW16A
Description
HCS08 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08AW16AE0CFT
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
S9S08AW16AE0CLC
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
S9S08AW16AE0CLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S08AW16AE0CLDR
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
S9S08AW16AE0MLC
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S08AW16AE0MLD
Manufacturer:
Freescal
Quantity:
12
Part Number:
S9S08AW16AE0MLD
Manufacturer:
FREESCALE
Quantity:
18 240
Part Number:
S9S08AW16AE0MLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
S9S08AW16AE0MLD
Manufacturer:
FREESCALE
Quantity:
18 240
MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS
OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The
master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back
high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input
of a slave.
When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not
defined until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto
the MOSI output of the master and the MISO output of the slave. The next SPSCK edge causes both the
master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the
third SPSCK edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled,
and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the
master and slave, respectively. When CHPA = 1, the slave’s SS input is not required to go to its inactive
high level between transfers.
Figure 12-11
shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last
SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting
Freescale Semiconductor
(MISO OR MOSI)
(MASTER OUT)
(REFERENCE)
(SLAVE OUT)
SAMPLE IN
MSB FIRST
BIT TIME #
(CPOL = 0)
(CPOL = 1)
LSB FIRST
(MASTER)
(SLAVE)
SS OUT
SPSCK
SPSCK
SS IN
MOSI
MISO
shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are
Figure 12-10. SPI Clock Formats (CPHA = 1)
BIT 7
BIT 0
1
MC9S08AC16 Series Data Sheet, Rev. 8
BIT 6
BIT 1
2
...
...
...
BIT 2
BIT 5
6
Serial Peripheral Interface (S08SPIV3)
BIT 1
BIT 6
7
BIT 0
BIT 7
8
221

Related parts for S9S08AW16A