LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 213

• Manufacturer Part Number: LM3S328-IQC20-A0
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

April 27, 2007
Reset
Reset
Type
Type
Bit/Field
ADC Interrupt Mask (ADCIM)
Offset 0x008
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to
controller interrupts. The raw interrupt signal for each Sample Sequencer can be masked
independently.
RO
RO
30
14
0
0
reserved
MASK3
MASK2
MASK1
MASK0
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
be changed.
Specifies whether the raw interrupt signal from Sample
Sequencer 3 (ADCRIS register INR3 bit) is promoted to a
controller interrupt. If set, the raw interrupt signal is promoted to
a controller interrupt. Otherwise, it is not.
Specifies whether the raw interrupt signal from Sample
Sequencer 2 (ADCRIS register INR2 bit) is promoted to a
controller interrupt. If set, the raw interrupt signal is promoted to
a controller interrupt. Otherwise, it is not.
Specifies whether the raw interrupt signal from Sample
Sequencer 1 (ADCRIS register INR1 bit) is promoted to a
controller interrupt. If set, the raw interrupt signal is promoted to
a controller interrupt. Otherwise, it is not.
Specifies whether the raw interrupt signal from Sample
Sequencer 0 (ADCRIS register INR0 bit) is promoted to a
controller interrupt. If set, the raw interrupt signal is promoted to
a controller interrupt. Otherwise, it is not.
Reserved bits return an indeterminate value, and should never
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
MASK3
R/W
RO
19
0
3
0
MASK2
LM3S328 Data Sheet
R/W
RO
18
0
2
0
MASK1
R/W
RO
17
0
1
0
MASK0
R/W
RO
16
0
0
0
213