LM3S328-IQC20-A0 ETC2 [List of Unclassifed Manufacturers], LM3S328-IQC20-A0 Datasheet - Page 211
LM3S328-IQC20-A0
Manufacturer Part Number
LM3S328-IQC20-A0
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S328-IQC20-A0.pdf
(371 pages)
- Current page: 211 of 371
- Download datasheet (3Mb)
April 27, 2007
Reset
Reset
Type
Type
Bit/Field
31:4
ADC Active Sample Sequencer (ADCACTSS)
Offset 0x000
3
2
1
0
RO
RO
31
15
0
0
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000
This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be
enabled/disabled independently.
RO
RO
30
14
0
0
reserved
ASEN3
ASEN2
ASEN1
ASEN0
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
Reset
0
0
reserved
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never be
changed.
Specifies whether Sample Sequencer 3 is enabled. If set, the
sample sequence logic for Sequencer 3 is active. Otherwise, the
Sequencer is inactive.
Specifies whether Sample Sequencer 2 is enabled. If set, the
sample sequence logic for Sequencer 2 is active. Otherwise, the
Sequencer is inactive.
Specifies whether Sample Sequencer 1 is enabled. If set, the
sample sequence logic for Sequencer 1 is active. Otherwise, the
Sequencer is inactive.
Specifies whether Sample Sequencer 0 is enabled. If set, the
sample sequence logic for Sequencer 0 is active. Otherwise, the
Sequencer is inactive.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
ASEN3
R/W
RO
19
0
3
0
LM3S328 Data Sheet
ASEN2
R/W
RO
18
0
2
0
ASEN1
R/W
RO
17
0
1
0
ASEN0
R/W
RO
16
0
0
0
211
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