M30245_06 RENESAS [Renesas Technology Corp], M30245_06 Datasheet - Page 254

• Manufacturer Part Number: M30245_06
• Description: RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Figure 2.10.5. Example of operation of one-shot transfer mode
BCLK
Address bus
RD signal
WR signal
Data bus
Write signal to
software DMAi
request bit
DMAi
request bit
DMA transfer
counter
DMAi
interrupt
request bit
DMAi
enable bit
Operation (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
2.10.2 Operation of DMAC (one-shot transfer mode)
In one-shot transfer mode, choose functions from the items shown in Table 2.10.1. Operations of the
circled items are described below. Figure 2.10.5 shows an example of operation and Figure 2.10.6
shows the set-up procedure.
• In the case in which the number of transfer times is set to 2.
Table 2.10.1. Choosed functions
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
(3) If the DMA transfer counter underflows, the DMA enable bit changes to “0” and DMA transfer
Transfer space
Unit of transfer
CPU use
Indeterminate
transfer request signal.
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 1 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
is completed. The DMA interrupt request bit changes to “1” simultaneously.
(1) Request signal for a DMA transfer occurs
Item
CPU use
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O
O
Source
(2) Data transfer begins
Source
Destination
Fixed address from fixed address
8 bits
16 bits
Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
01
16
Destination
Dummy
cycle
Dummy
cycle
00
CPU use
16
CPU use
Set-up
Source
Source
Destination
(3) Underflow
Destination
Dummy
cycle
Cleared to “0” when interrupt request is
accepted, or cleared by software
Dummy
cycle
FF
16
CPU use
CPU use
2. DMAC