M30245_06 RENESAS [Renesas Technology Corp], M30245_06 Datasheet - Page 193

• Manufacturer Part Number: M30245_06
• Description: RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
•TOGGLE_INIT bit
•FLUSH bit
•ISO bit
•SEND_STALL bit
•AUTO_CLR bit
The configuration of USB endpoint x OUT control and status register is shown in Figure 2.8.40.
This bit initializes data toggle sequence bit in bulk/interrupt transfer.
With this bit being set to “1”, the PID of the next packet to be received from the host CPU becomes
DATA0. When initialization of the data toggle sequence is requested from the host CPU at the time of
configuration, etc., set TOGGLE_INIT bit and initialize PID to DATA0 before starting the OUT end-
point communication.
At this time, the internal read/write counter of OUT FIFO is also initialized.
On completing PID initialization, this bit is automatically cleared to “0”.
This bit controls the OUT FIFO packet.
With this bit being set to “1”, one buffer data received in OUT FIFO is flushed out from the OUT FIFO.
- When there is one buffer data in OUT FIFO, the OUT FIFO becomes empty.
- When there are two buffer data in OUT FIFO, the older data is flushed out from the OUT FIFO.
The receive data may be destroyed if this bit is set to “1” during USB transfer.
Read the OUT_BUF_STS1 and OUT_BUF_STS0 flags and confirm that there are data in the OUT
FIFO, and then, set this bit to “1”.
On completing one buffer data destruction, this bit is automatically cleared to “0”.
Set this bit to “1” in order to use an endpoint in isochronous transfer. Set this bit to “0” in order to use
an endpoint in bulk/interrupt transfer.
This bit controls the STALL response to the host CPU in bulk transfer/interrupt transfer.
Set this bit to “1” when the OUT endpoint is in STALL state. While this bit is set to “1”, the USB
function control unit transmits the STALL handshake concerning all the OUT transactions to the host
CPU. When the OUT endpoint has returned from STALL state, clear this bit by writing “0”. The OUT
endpoint communication is resumed.
This bit controls setting of CLR_OUT_BUF_RDY bit.
With this bit being set to “1”, when one receive buffer data is read from OUT FIFO, the OUT_BUF_STS1
and OUT_BUF_STS0 flags are automatically updated without CLR_OUT_BUF_RDY bitbeing set to
“1”. With this bit being set to “0”, on completing one receive buffer data fetch from OUT FIFO,
CLR_OUT_BUF_RDY bit has to be set to “1” by software.
At this time, the OUT_BUF_STS1 and OUT_BUF_STS0 flags are updated from “11
At this time, the OUT_BUF_STS1 and OUT_BUF_STS0 flags are updated from “11
“00
indicates that one more buffer data is left inside the OUT FIFO).
2
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