M30245_06 RENESAS [Renesas Technology Corp], M30245_06 Datasheet - Page 185

• Manufacturer Part Number: M30245_06
• Description: RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES
• Manufacturer: RENESAS [Renesas Technology Corp]

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(3) Control Transfer: Endpoint 0 Transmit
The endpoint 0 transmits the packet data to the host CPU in the data stage by the control read after
completion of receive request analysis process in the setup stage.
Write one packet data to be transmitted in IN FIFO. Every time that one-byte data is written in IN FIFO,
the internal write pointer is automatically incremented by “2” in word access and by “1” in byte access.
The contents of internal write pointer cannot be read. When the data write in IN FIFO is completed, set
IN_BUF_RDY flag to “1” by setting “1” to SET_IN_BUF_RDY bit. When an empty packet (with 0 data
length) is transmitted, data is not written in IN FIFO and SET_IN_BUF_RDY bit is set to “1”.
At this time, one packet transmission is prepared and is transmitted by the USB function control unit in
the next IN token.
The IN_BUF_RDY flag is automatically set to “0”, when one packet data transmission is completed to
the host CPU (or on receiving ACK) or when the SETUP_END flag is set to “1”. After writing the last
data packet in IN FIFO, set SET_IN_BUF_RDY bit to “1” and, simultaneously set SET_DATA_END bit
to “1”. Both the IN_BUF_RDY flag and DATA_END flag are set to “1”. When the DATA_END flag
becomes “1” after completion of transmission of the last data packet, the USB function control unit
proceeds to the status phase processing.
When the status phase is completed, the DATA_END flag is cleared to “0”.
Manage the stage of control transfer by software.
1: Check that the packet data does not exist in IN FIFO (the IN_BUF_RDY flag is “0”) before writing
2: The data is written in IN FIFO based on the amount specified on the SETUP stage.
3: With SET_IN_BUF_RDY bit being set to “1”, one packet transmission is prepared, and the next
Example of one packet data transmit procedure
the data of the 2nd packet and after of data stage.
When an empty packet (with 0 data length) is transmitted, the data is not written in IN FIFO.
The subsequent stage and operation are determined.
stage control is managed.
• For shifting into the status stage even if the next data to be transmitted does not exist, simulta-
• When the next empty packet is transmitted, set SET_IN_BUF_RDY bit to “1” and continue
neously set SET_IN_BUF_RDY bit and SET_DATA_END bit.
transmitting processing.
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2. USB function