STR91XFA STMICROELECTRONICS [STMicroelectronics], STR91XFA Datasheet - Page 20

• Manufacturer Part Number: STR91XFA
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Functional overview
2.13.4 External RESET_INn pin
2.13.5 Power-up
2.13.6 JTAG debug command
2.13.7 Tamper detection
2.14
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peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled by
firmware as a watchdog, this timer will cause a system reset if firmware fails to periodically
reload this timer before the terminal count of 0x0000 occurs, ensuring firmware sanity. The
watchdog function is off by default after a reset and must be enabled by firmware.
This input signal is active-low with hystereses (V
reset signals on the circuit board (such as closure to ground from a push-button) may be
connected directly to the RESET_INn pin, but an external pull-up resistor to V
present as there is no internal pullup on the RESET_INn pin.
A valid active-low input signal of t
reset within the STR91xFA. There is also a RESET_OUTn pin on the STR91xFA that can drive
other system components on the circuit board. RESET_OUTn is active-low and has the same
timing of the Power-On-Reset (POR) shown next, t
The LVD circuitry will always generate a global reset when the STR91xFA powers up, meaning
internal reset is active until V
condition has a duration of t
0x0000.0000 in Flash memory. It is not possible for the CPU to boot from any other source
other than Flash memory.
When the STR91xFA is in JTAG debug mode, an external device which controls the JTAG
interface can command a system reset to the STR91xFA over the JTAG channel.
On 128-pin and 144-ball STR91xFA devices only, there is a tamper detect input pin,
TAMPER_IN, used to detect and record the time of a tamper event on the end product such as
malicious opening of an enclosure, unwanted opening of a panel, etc. The activation mode of
the tamper pin is programmable to one of two modes. One is Normally Closed/Tamper Open,
the other mode will detect when a signal on the tamper input pin is driven from low-to-high, or
high-to-low depending on firmware configuration. Once a tamper event occurs, the RTC time
(millisecond resolution) and the date are recorded in the RTC unit. Simultaneously, the SRAM
standby voltage source will be cut off to invalidate all SRAM contents. Tamper detection control
and status logic are part of the RTC unit.
Real-time clock (RTC)
The RTC combines the functions of a complete time-of-day clock (millisecond resolution) with
an alarm programmable up to one month, a 9999-year calender with leap-year support,
periodic interrupt generation from 1 to 512 Hz, tamper detection (described in
and an optional clock calibration output on the JRTCK pin. The time is in 24 hour mode, and
time/calendar values are stored in binary-coded decimal format.
The RTC also provides a self-isolation mode that is automatically activated during power down.
This feature allows the RTC to continue operation when V
POR
DDQ
, after which the CPU will fetch its first instruction from address
RINMIN
and V
DD
duration on the RESET_INn pin will cause a system
are both above the LVD thresholds. This POR
RHYS
POR
). Other open-drain, active-low system
.
DDQ
and V
DD
are absent, as long as
DDQ
Section
must be
STR91xFA
2.13.7),