ST7FLITE02 STMICROELECTRONICS [STMicroelectronics], ST7FLITE02 Datasheet - Page 47

• Manufacturer Part Number: ST7FLITE02
• Description: 8-BIT MICROCONTROLLER WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
10.3 UNUSED I/O PINS
Unused I/O pins must be connected to fixed volt-
age levels. Refer to
10.4 LOW POWER MODES
Table 11. Port Configuration
WAIT
HALT
Mode
Port A
Port B
Port
No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.
PA7
PA6:1
PA0
PB4
PB3
PB2:1
PB0
Pin name
Section
Description
13.8.
OR = 0
floating
floating
floating
floating
floating
floating
floating
Input (DDR=0)
pull-up interrupt
pull-up interrupt
pull-up interrupt
pull-up interrupt
10.5 INTERRUPTS
The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the interrupt mask in
the CC register is not active (RIM instruction).
10.6 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 29. Interrupt I/O Port State Transitions
The I/O port register configurations are summa-
rised as follows.
floating/pull-up
External interrupt on
selected external
event
OR = 1
pull-up
pull-up
pull-up
Interrupt Event
interrupt
INPUT
01
(reset state)
floating
INPUT
00
open drain
open drain
open drain
open drain
open drain
open drain
open drain
OR = 0
Event
Flag
ST7LITE0x, ST7LITESx
Figure 29
-
Output (DDR=1)
open-drain
Control
Enable
OUTPUT
DDRx
ORx
Bit
10
XX
Other transitions
= DDR, OR
from
Wait
Exit
Yes
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
push-pull
OR = 1
OUTPUT
push-pull
11
47/125
from
Exit
Halt
Yes
1