ST7FLITE02 STMICROELECTRONICS [STMicroelectronics], ST7FLITE02 Datasheet - Page 123

• Manufacturer Part Number: ST7FLITE02
• Description: 8-BIT MICROCONTROLLER WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

17 REVISION HISTORY
Table 26. Revision History
21-July-06
27-Oct-04
Date
Revision
3
4
Revision number incremented from 2.5 to 3.0 due to Internal Document Management Sys-
tem change
Changed all references of ADCDAT to ADCDR
Added EMU3 Emulator Programming Capability in
Clarification of read-out protection
Altered note 1 for
Alteration of f
on page 91
Removed sentence relating to an effective change only after overflow for CK[1:0],
Added illegal opcode detection to page 1,
Clarification of Flash read-out protection,
f
Updated F
section 8.4.4 on page
the AVDF bit is set”
Socket Board development kit details added in
PWM Signal diagram corrected,
Corrected count of reserved bits between 003Bh to 007Fh,
Inserted note that RCCR0 and RCCR1 are erased if read-only flag is reset,
page 25
Added QFN20 package
Modified
Changed Read operation paragraph in
Modified note below
Modified note to
Added note on illegal opcode reset to
Added note 2 to EICR description on
Modified External Interrupt Function in
Changed text on input capture before
Modified text in
Added important note in
Changed note 1 in
Modified values in
Modified note 2 in
Added note on clock stability and frequency accuracy to
13.3.4.2 on page
115
Changed I
Added note in
Changed
102
Changed
Modified
Added ECOPACK information to
Modified
Modified
Modified
Updated option list on
Changed
Removed erratasheet section
Added
Revision History continued overleaf ...
PLL
value of 1MHz quoted as Typical instead of a Minimum in
(device works correctly without these components)
Section 16.4
section 2 on page 6
Figure 78
Figure 86 on page 111
Table 20 on page 113
section 15.2 on page 116
Figure 75 on page 102
section 13.10.1 on page 103
section 15.3 on page 118
S
SCK
value and note 2 in
CPU
Figure 61 on page 96
in
section 11.1.5 on page 51
section 7.1 on page 25
section 13.10.1 on page 103
87,
for SLOW and SLOW-WAIT modes in
section 13.2.3 on page 83
section 13.3.4.1 on page 86
section 13.2.2 on page 83
section 13.2 on page 83
(CPHA=1) and
and
Figure 9 on page 18
section 7.1 on page 25
37: Changed wording in AVDIE and AVDF bit descriptions to “...when
page 117
section 11.3.3.3 on page 63
section 16.5 on page 122
section 13.8.1 on page 96
and removed EMC protection circuitry in
Figure 35 on page 56
(A1 and A swapped in the diagram)
Description of changes
section 14 on page 110
Figure 79 on page 104
page 32
section 7.4.1 on page 28
section 11.1.4 on page 51
section 10.2.1 on page 43
(t
section 5.3 on page 17
su(SS),
section 4.5.1 on page 15
and modified
section 8.4 on page
removing references to RESET
and to OSC option bit in
to F
t
and
Table 24 on page 115
v(MO) and
CPU
Table 23
section 13.3.4.2 on page 87
/4 and F
section 13.3.4.1 on page
section 5.5 on page 19
Section 13.4.1
t
h(MO)
(t
Table 2 on page 11
v(MO) ,
ST7LITE0x, ST7LITESx
section 14.3.5.2 on page 92
)
33,
CPU
t
section 12 on page 75
/2
h(MO)
Section 15.1
table and
)
Figure 76 on page
section 7.1 on
86,
Figure 58
page 57
on
section
123/125
page