LPC2919 PHILIPS [NXP Semiconductors], LPC2919 Datasheet - Page 44

• Manufacturer Part Number: LPC2919
• Description: ARM9 microcontroller with CAN and LIN
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
LPC2917_19_1
Preliminary data sheet
Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be
connected to either a fractional divider (FDIV0..6) or to one of the outputs of the PLL or to
LP_OSC/crystal oscillator directly. BASE_SAFE_CLK and BASE_PCR_CLK can use only
LP_OSC as source.
The fractional dividers can be connected to one of the outputs of the PLL or directly to
LP_OSC/crystal Oscillator.
The PLL can be connected to the crystal oscillator.
In this way every output generating the base clocks can be configured to get the required
clock. Multiple output generators can be connected to the same primary or secondary
clock source, and multiple secondary clock sources can be connected to the same PLL
output or primary clock source.
Invalid selections/programming - connecting the PLL to an FDIV or to one of the PLL
outputs itself for example - will be blocked by hardware. The control register will not be
written, the previous value will be kept, although all other fields will be written with new
data. This prevents clocks being blocked by incorrect programming.
Default Clock Sources:
connected to LP_OSC at reset. In this way the device runs at a low frequency after reset.
It is recommended to switch BASE_SYS_CLK to a high-frequency clock generator as
(one of) the first step(s) in the boot code after verifying that the high-frequency clock
generator is running.
Fig 13. Structure of the clock generation scheme
OSC1M
XO50M
Rev. 1.01 — 15 November 2007
Every secondary clock generator or output generator is
PLL160M
ARM9 microcontroller with CAN and LIN
clkout120 /
clkout240
clkout /
Control
outputs
Output
Clock
LPC2917/19
© NXP B.V. 2007. All rights reserved.
FDIV0..6
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