LPC2460FET208 PHILIPS [NXP Semiconductors], LPC2460FET208 Datasheet - Page 43

• Manufacturer Part Number: LPC2460FET208
• Description: Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
LPC2460_0
Preliminary data sheet
7.25.3 Brownout detection
7.25.4 AHB bus
7.25.5 External interrupt inputs
7.25.6 Memory mapping control
7.26 Emulation and debugging
The LPC2460 includes 2-stage monitoring of the voltage on the V
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register.
The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if
this reset source is enabled in software) to inactivate the LPC2460 when the voltage on
the V
at which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
The LPC2460 implements two AHB buses in order to allow the Ethernet block to operate
without interference caused by other system activity. The primary AHB, referred to as
AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and
16 kB SRAM.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters
with access to AHB2 are the ARM7 and the Ethernet block.
The LPC2460 includes up to 68 edge sensitive interrupt inputs combined with up to four
level sensitive external interrupt inputs as selectable pin functions. The external interrupt
inputs can optionally be used to wake up the processor from Power-down mode.
The memory mapping control alters the mapping of the interrupt vectors that appear at the
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot
ROM, the SRAM, or external memory. This allows code running in different memory
spaces to have control of the interrupts.
The LPC2460 support emulation and debugging via a JTAG serial port. A trace port allows
tracing program execution. Debugging and trace functions are multiplexed only with
GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface
peripherals residing on other pins are available during the development and debugging
phase as they are when the application is run in the embedded system itself.
DD(3V3)
pins falls below 2.65 V. The BOD circuit maintains this reset down below 1 V,
Rev. 00.01 — 5 October 2007
Fast communication chip
DD(3V3)
LPC2460
© NXP B.V. 2007. All rights reserved.
pins. If this
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