LPC2460FET208 PHILIPS [NXP Semiconductors], LPC2460FET208 Datasheet

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LPC2460FET208

Manufacturer Part Number
LPC2460FET208
Description
Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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1. General description
2. Features
NXP Semiconductors designed the LPC2460 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2460 is fashless. The LPC2460 can execute both 32-bit ARM
and 16-bit Thumb instructions. Support for the two instruction sets means engineers can
choose to optimize their application for either performance or code size at the sub-routine
level. When the core executes instructions in Thumb state it can reduce code size by
more than 30 % with only a small loss in performance while executing instructions in ARM
state maximizes core performance.
The LPC2460 microcontroller is ideal for multi-purpose communication applications. It
incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed
Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I
interfaces, and an I
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for
Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an
External Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 160 fast GPIO lines. The LPC2460 connects 64 of the GPIO pins
to the hardware based Vector Interrupt Controller (VIC) that means these external inputs
can generate edge-triggered interrupts. All of these features make the LPC2460
particularly suitable for industrial control and medical systems.
LPC2460
Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, USB 2.0
device/host/OTG, external memory interface
Rev. 00.01 — 5 October 2007
ARM7TDMI-S processor, running at up to 72 MHz.
98 kB on-chip SRAM includes:
Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, and USB DMA with no contention.
EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as Single Data Rate SDRAM.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
64 kB of SRAM on the ARM local bus for high performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
16 kB SRAM for general purpose DMA use also accessible by the USB.
2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
2
S interface. Supporting this collection of serial communications
Preliminary data sheet
2
C

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LPC2460FET208 Summary of contents

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LPC2460 Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 00.01 — 5 October 2007 1. General description NXP Semiconductors designed the LPC2460 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include ...

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NXP Semiconductors General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I and SD/MMC interface as well as for memory-to-memory transfers. Serial Interfaces: Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on ...

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... Type number Package Name Description plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm LPC2460FBD208 LQFP208 LPC2460FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 × 0.7 mm SOT950-1 4.1 Ordering options Table 2. Ordering options Type number Flash ...

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NXP Semiconductors 5. Block diagram LPC2460 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 160 PINS TOTAL AHB2 16 kB ETHERNET SRAM MII/RMII MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × ...

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... Preliminary data sheet 1 LPC2460FBD208 52 002aad314 ball A1 index area LPC2460FET208 Transparent top view Pin Symbol V 3 P1[0]/ENET_TXD0 SSIO P1[9]/ENET_RXD0 7 P1[14]/ENET_RX_ER P1[3]/ENET_TXD3/ 11 P4[15]/A15 MCICMD/PWM0[2] P1[11]/ENET_RXD2/ 15 P0[8]/I2STX_WS/ MCIDAT2/PWM0[6] MISO1/MAT2[2] Rev. 00.01 — 5 October 2007 ...

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NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 17 P1[5]/ENET_TX_ER/ MCIPWR/PWM0[3] Row B 1 P3[2]/ P1[1]/ENET_TXD1 6 9 P4[25]/ DD(3V3) 17 P2[0]/PWM1[1]/TXD1/ TRACECLK Row C 1 P3[13]/D13 2 5 P3[9]/D9 ...

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NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Row H 1 P0[23]/AD0[0]/ 2 I2SRX_CLK/CAP3[ SSIO Row J 1 P3[6]/ P0[16]/RXD1/ 15 SSEL0/SSEL Row K 1 VREF 2 14 P4[22]/A22/ 15 TXD2/MISO1 ...

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NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol 13 P2[17]/RAS 14 17 P4[20]/A20/ SDA2/SCK1 Row T 1 P0[27]/SDA0 SSIO 9 P1[24]/USB_RX_DM1/ 10 PWM1[5]/MOSI0 13 P1[28]/USB_SCL1/ 14 PCAP1[0]/MAT0[0] 17 P2[11]/EINT1/ MCIDAT1/I2STX_CLK Row U ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[3]/RXD0 204 D6 [1] P0[4]/ 168 B12 I2SRX_CLK/ RD2/CAP2[0] [1] P0[5]/ 166 C12 I2SRX_WS/ TD2/CAP2[1] [1] P0[6]/ 164 D13 I2SRX_SDA/ SSEL1/MAT2[0] [1] P0[7]/ 162 C13 I2STX_CLK/ SCK1/MAT2[1] [1] ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [2] [2] P0[12 USB_PPWR2/ MISO1/AD0[6] [2] [2] P0[13 USB_UP_LED2/ MOSI1/AD0[7] [1] [1] P0[14 USB_HSTEN2/ USB_CONNECT2/ SSEL1 [1] [1] P0[15]/TXD1/ 128 J16 SCK0/SCK [1] [1] ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P0[21]/RI1/ 118 M16 MCIPWR/RD1 [1] P0[22]/RTS1/ 116 N17 MCIDAT0/TD1 [2] [2] P0[23]/AD0[0 I2SRX_CLK/ CAP3[0] [2] [2] P0[24]/AD0[1 I2SRX_WS/ CAP3[1] [2] [2] P0[25]/AD0[2 I2SRX_SDA/ ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[0]/ 196 A3 ENET_TXD0 [1] [1] P1[1]/ 194 B5 ENET_TXD1 [1] [1] P1[2]/ 185 D9 ENET_TXD2/ MCICLK/ PWM0[1] [1] P1[3]/ 177 A10 ENET_TXD3/ MCICMD/ PWM0[2] [1] [1] P1[4]/ ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[13]/ 147 D16 ENET_RX_DV [1] [1] P1[14]/ 184 A7 ENET_RX_ER [1] [1] P1[15]/ 182 A8 ENET_REF_CLK/ ENET_RX_CLK [1] P1[16]/ 180 D10 ENET_MDC [1] [1] P1[17]/ 178 A9 ENET_MDIO [1] ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[25]/ 80 T10 USB_LS1/ USB_HSTEN1/ MAT1[1] [1] P1[26]/ 82 R10 USB_SSPND1/ PWM1[6]/ CAP0[0] [1] [1] P1[27]/ 88 T12 USB_INT1/ USB_OVRCR1/ CAP0[1] [1] [1] P1[28]/ 90 T13 USB_SCL1/ PCAP1[0]/ ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[2]/PWM1[3]/ 150 D15 CTS1/ PIPESTAT1 [1] P2[3]/PWM1[4]/ 144 E16 DCD1/ PIPESTAT2 [1] P2[4]/PWM1[5]/ 142 D17 DSR1/ TRACESYNC [1] [1] P2[5]/PWM1[6]/ 140 F16 DTR1/ TRACEPKT0 [1] P2[6]/PCAP1[0]/ 138 E17 RI1/TRACEPKT1 ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [6] [6] P2[11]/EINT1/ 108 T17 MCIDAT1/ I2STX_CLK [6] P2[12]/EINT2/ 106 N14 MCIDAT2/ I2STX_WS [6] [6] P2[13]/EINT3/ 102 T16 MCIDAT3/ I2STX_SDA [6] P2[14]/CS2/ 91 R12 CAP2[0]/SDA1 [6] P2[15]/CS3/ 99 P13 CAP2[1]/SCL1 ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P2[23]/DYCS3 CAP3[1]/SSEL0 [1] [1] P2[24 CKEOUT0 [1] [1] P2[25 CKEOUT1 [1] [1] P2[26 CKEOUT2/ MAT3[0]/MISO0 [1] [1] P2[27 ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P3[5]/ [1] [1] P3[6]/ [1] [1] P3[7]/ [1] [1] P3[8]/D8 191 D8 [1] [1] P3[9]/D9 199 C5 [1] [1] P3[10]/D10 205 B2 ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P3[20]/D20/ 167 A13 PWM0[5]/DSR1 [1] P3[21]/D21/ 175 C10 PWM0[6]/DTR1 [1] [1] P3[22]/D22/ 195 C6 PCAP0[0]/RI1 [1] [1] P3[23]/D23 CAP0[0]/ PCAP1[0] [1] [1] P3[24]/D24 CAP0[1]/ PWM1[1] ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P3[30]/D30 MAT1[1]/ RTS1 [1] [1] P3[31]/D31 MAT1[2] P4[0] to P4[31] [1] [1] P4[0]/ [1] P4[1]/A1 79 U10 [1] [1] P4[2]/A2 83 T11 ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P4[15]/A15 173 A11 [1] P4[16]/A16 101 U17 [1] P4[17]/A17 104 P14 [1] P4[18]/A18 105 P15 [1] P4[19]/A19 111 P16 [1] P4[20]/A20/ 109 R17 SDA2/SCK1 [1] P4[21]/A21/ 115 M15 ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P4[29]/BLS3/ 176 B10 MAT2[1]/RXD3 [1] [1] P4[30]/CS0 187 B7 [1] [1] P4[31]/CS1 193 A4 [8] [8] ALARM 37 N1 USB_D− [1] [1] DBGEN 9 F4 [1] [1] ...

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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball V 15, 60, G3, DD(3V3) 71, 89, P6, P8, 112, U13, 125, P17, 146, K16, 165, C17, 181, B13, [11] 198 C9, [11 30, 117, J4, L14, [12] ...

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NXP Semiconductors memory, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2460 implements two AHB buses in order to allow the Ethernet block to operate ...

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NXP Semiconductors SRAM block serving as a buffer for the Ethernet controller and SRAM associated with the second AHB bus can be used both for data and code storage, too. The 2 kB RTC ...

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NXP Semiconductors 4.0 GB 3.75 GB 3.5 GB 2.0 GB 1.0 GB 0.0 GB Fig 4. LPC2460 memory map 7.4 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The ...

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NXP Semiconductors service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is ...

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NXP Semiconductors – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. ...

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NXP Semiconductors • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set ...

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NXP Semiconductors 7.9 Ethernet The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or ...

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NXP Semiconductors – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is ...

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NXP Semiconductors 7.10.2.1 Features • OHCI compliant. • Two downstream ports. • Supports per-port power switching. 7.10.3 USB OTG Controller USB OTG (On-The-Go supplement to the USB 2.0 specification that augments the capability of existing mobile devices and ...

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NXP Semiconductors • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • Full CAN messages can generate interrupts. 7.12 10-bit ADC The LPC2460 contains one ADC single 10-bit successive approximation ADC with eight channels. ...

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NXP Semiconductors • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control ...

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NXP Semiconductors 7.17.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11. • Conforms to ...

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NXP Semiconductors 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can ...

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NXP Semiconductors 7.21 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2460. The Timer is designed to count cycles of ...

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NXP Semiconductors • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled ...

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NXP Semiconductors 7.23.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and ...

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NXP Semiconductors 7.24.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU. 7.24.2 PLL The PLL accepts ...

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NXP Semiconductors PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine ...

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NXP Semiconductors On the LPC2460, I/O pads are powered by the 3 DD(DCDC)(3V3) the CPU and most of the peripherals. Although both the I/O pad ring and the core require a 3.3 V supply, different powering schemes ...

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NXP Semiconductors 7.25.3 Brownout detection The LPC2460 includes 2-stage monitoring of the voltage on the V voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in ...

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NXP Semiconductors 7.26.1 EmbeddedICE The EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug Protocol commands ...

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NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad ...

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NXP Semiconductors 9. Static characteristics Table 7. Static characteristics − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage ...

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NXP Semiconductors Table 7. Static characteristics …continued − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I active mode DC-to-DC DD(DCDC)act(3V3) converter supply current (3 power-down mode DD(DCDC)pd(3V3) ...

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NXP Semiconductors Table 7. Static characteristics …continued − ° ° +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V differential input DI sensitivity V differential common CM mode voltage range V single-ended ...

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NXP Semiconductors [1] Conditions 3.3 V. SSA DDA [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error ( the difference between the actual step width and ...

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NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity ...

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NXP Semiconductors AD0[y] SAMPLE Fig 6. Suggested ADC interface - LPC2460 AD0[y] pin LPC2460_0 Preliminary data sheet LPC2XXX R vsi 20 kΩ AD0[ Rev. 00.01 — 5 October 2007 LPC2460 Fast communication chip V ...

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NXP Semiconductors 10. Dynamic characteristics Table 9. Dynamic characteristics of USB pins (full-speed) Ω pF 1 Symbol Parameter t rise time r t fall time f t differential ...

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NXP Semiconductors Table 10. Dynamic characteristics − ° ° +85 C for commercial applications; V amb Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t ...

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NXP Semiconductors 10.1 Timing − 0 0.2V 0.2V DD 0.45 V Fig 7. External clock timing t PERIOD crossover point differential data lines differential data to n × t Fig 8. Differential data-to-EOP transition skew and EOP ...

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NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC24XX Fig 10. LPC2460 USB interface on a self-powered device LPC24XX Fig 11. LPC2460 USB interface on a bus-powered device LPC2460_0 Preliminary data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch ...

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NXP Semiconductors RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 12. LPC2460 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2460_0 Preliminary data sheet ...

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NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 13. LPC2460 USB OTG port configuration: VP_VM mode LPC2460_0 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW ...

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NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 14. LPC2460 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2460_0 Preliminary data sheet Ω 33 Ω ...

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NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 15. LPC2460 USB OTG port configuration: USB port 1 host, USB port 2 host 11.2 Suggested boot memory interface solutions “a_m“ and “a_b“ in ...

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NXP Semiconductors Fig 17. Booting from a single 16-bit memory chip LPC2460_0 Preliminary data sheet CS1 16-bit BLS[1] MEMORY LB BLS[0] IO[15:0] D[15:0] A[a_m:0] A[a_b:1] 002aad323 Rev. 00.01 — 5 October 2007 LPC2460 Fast ...

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NXP Semiconductors 12. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original ...

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NXP Semiconductors TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ...

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NXP Semiconductors 13. Abbreviations Table 11. Acronym ADC AHB AMBA APB ATX BLS BOD CAN DAC DCC DMA DSP EOP ETM GPIO IrDA JTAG MII PHY PLL PWM RMII SD/MMC SE0 SPI SSI SSP TTL UART USB LPC2460_0 Preliminary data ...

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NXP Semiconductors 14. Revision history Table 12. Revision history Document ID Release date LPC2460_0.01 <tbd> LPC2460_0 Preliminary data sheet Data sheet status Change notice Preliminary Rev. 00.01 — 5 October 2007 LPC2460 Fast communication chip Supersedes © NXP B.V. 2007. ...

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NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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NXP Semiconductors 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15.3 Disclaimers . . . . . ...

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