LPC3230 NXP [NXP Semiconductors], LPC3230 Datasheet - Page 41

• Manufacturer Part Number: LPC3230
• Description: 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
8. Basic architecture
LPC3220_30_40_50_1
Preliminary data sheet
The LPC3220/30/40/50 is a general purpose ARM926EJ-S 32-bit microprocessor with a
32 kB instruction cache and a 32 kB data cache. The microcontroller offers high
performance and very low power consumption. The ARM architecture is based on RISC
principles, which results in the instruction set and related decode mechanism being much
simpler than equivalent micro programmed CISCs. This simplicity results in a high
instruction throughput and impressive real-time interrupt response from a small and
cost-effective processor core.
The ARM926EJ-S core employs a 5-stage pipeline so processing and memory system
accesses can occur continuously. At any one point in time, several operations are in
progress: subsequent instruction fetch, next instruction decode, instruction execution,
memory access, and write-back. The combination of architectural enhancements gives
the ARM9 about 30 % better performance than an ARM7 running at the same clock rate:
The ARM926EJ-S processor also employs an operational state known as Thumb, which
makes it ideally suited to high-volume applications with memory restrictions, or
applications where code density is an issue.
The key idea behind Thumb state is the use of a super-reduced instruction set.
Essentially, the ARM926EJ-S processor core has two instruction sets:
The Thumb set’s smaller 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining many of ARM’s 32-bit performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates using the same 32-bit register set as ARM code. Thumb code size is up to 65 %
smaller than ARM code size, and 160 % of the performance of an equivalent ARM
processor connected to a 16-bit memory system. Additionally, the ARM926EJ-S core
includes enhanced DSP instructions and multiplier, as well as an enhanced 32-bit MAC
block.
1. The standard 32-bit ARM set
2. The 16-bit Thumb set
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32-bit pulse-width (match) register
10-bit dead-time register and an associated 10-bit dead-time counter
32-bit capture register
Two PWM (match) outputs (pins MCOA0/1/2 and MCOB0/1/2) with opposite polarities
Period interrupt, pulse-width interrupt, and capture interrupt
Approximately 1.3 clocks per instruction for the ARM926 compared to 1.9 clocks per
instruction for ARM7TDMI.
Approximately 1.1 Dhrystone MIPS/MHz for the ARM926 compared to 0.9 Dhrystone
MIPS/MHz for ARM7TDMI.
Rev. 01 — 6 February 2009
LPC3220/30/40/50
16/32-bit ARM microcontrollers
© NXP B.V. 2009. All rights reserved.
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