LPC3230 NXP [NXP Semiconductors], LPC3230 Datasheet - Page 22

• Manufacturer Part Number: LPC3230
• Description: 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC3220_30_40_50_1
Preliminary data sheet
7.1.3.2 Embedded trace buffer
7.2 AHB matrix
The Embedded Trace Module (ETM) is connected directly to the ARM core. It compresses
the trace information and exports it through a narrow trace port. An internal Embedded
Trace Buffer (ETB) of 2048
debugger control. Data from the ETB is recovered by the debug software through the
JTAG port.
The trace contains information about when the ARM core switches between states.
Instruction shows the flow of execution of the processor and provides a list of all the
instructions that were executed. Instruction trace is significantly compressed by only
broadcasting branch addresses as well as a set of status signals that indicate the pipeline
status on a cycle by cycle basis. For data accesses either data or address or both can be
traced.
The LPC3220/30/40/50 has a multi-layer AHB matrix for inter-block communication. AHB
is an ARM defined high-speed bus, which is part of the ARM bus architecture. AHB is a
high-bandwidth low-latency bus that supports multi-master arbitration and a bus
grant/request mechanism. For systems that have only one (CPU), or two (CPU and DMA)
bus masters a simple AHB works well. However, if a system requires multiple bus masters
and the CPU needs access to external memory, a single AHB bus can cause a bottleneck.
To increase performance, the LPC3220/30/40/50 uses an expanded AHB architecture
known as Multi-layer AHB. A Multi-layer AHB replaces the request/grant and arbitration
mechanism used in a simple AHB with an interconnect matrix that moves arbitration out
toward the slave devices. Thus, if a CPU and a DMA controller want access to the same
memory, the interconnect matrix arbitrates between the two when granting access to the
memory. This advanced architecture allows simultaneous access by bus masters to
different resources with an increase in arbitration complexity. In this architectural
implementation, removing guaranteed central arbitration and allowing more than one bus
master to be active at the same time provides better overall microcontroller performance.
In the LPC3220/30/40/50, the multi-Layer AHB system has a separate bus for each of
seven AHB Masters:
There are no arbitration delays unless two masters attempt to access the same slave at
the same time.
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CPU data bus
CPU instruction bus
General purpose DMA Master 0
General purpose DMA Master 1
Ethernet controller
USB controller
LCD controller
Rev. 01 — 6 February 2009
24 bits captures the trace information under software
LPC3220/30/40/50
16/32-bit ARM microcontrollers
© NXP B.V. 2009. All rights reserved.
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